{"id":"https://openalex.org/W2111641757","doi":"https://doi.org/10.1109/ats.2003.1250849","title":"Designing multiple scan chains for systems-on-chip","display_name":"Designing multiple scan chains for systems-on-chip","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2111641757","doi":"https://doi.org/10.1109/ats.2003.1250849","mag":"2111641757"},"language":"en","primary_location":{"id":"doi:10.1109/ats.2003.1250849","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2003.1250849","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5098329598","display_name":"Quasem","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Quasem","raw_affiliation_strings":["Department of Electrical Engineering, University of Southern California, USA","Dept. of Electr. Eng., Univ. of Southern California, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Southern California, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Univ. of Southern California, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109496921","display_name":"Gupta","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gupta","raw_affiliation_strings":["Department of Electrical Engineering, University of Southern California, USA","Dept. of Electr. Eng., Univ. of Southern California, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Southern California, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Univ. of Southern California, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5098329598"],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":1.0062,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.77145641,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"424","last_page":"427"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.9650783538818359},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.818101704120636},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7042054533958435},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5535590052604675},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5254960656166077},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5216770172119141},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.4796024560928345},{"id":"https://openalex.org/keywords/chain","display_name":"Chain (unit)","score":0.412243127822876},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40392640233039856},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38912299275398254},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38516077399253845},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37676531076431274},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.22070229053497314},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1478855013847351},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12454411387443542}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.9650783538818359},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.818101704120636},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7042054533958435},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5535590052604675},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5254960656166077},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5216770172119141},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.4796024560928345},{"id":"https://openalex.org/C199185054","wikidata":"https://www.wikidata.org/wiki/Q552299","display_name":"Chain (unit)","level":2,"score":0.412243127822876},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40392640233039856},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38912299275398254},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38516077399253845},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37676531076431274},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.22070229053497314},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1478855013847351},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12454411387443542},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ats.2003.1250849","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2003.1250849","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2165642910","https://openalex.org/W2503952136","https://openalex.org/W4242912069","https://openalex.org/W6926824752"],"related_works":["https://openalex.org/W2117171289","https://openalex.org/W2127184179","https://openalex.org/W1852363244","https://openalex.org/W1501621551","https://openalex.org/W2001654810","https://openalex.org/W2172250424","https://openalex.org/W2012436574","https://openalex.org/W2105536286","https://openalex.org/W79379040","https://openalex.org/W2131620625"],"abstract_inverted_index":{"We":[0,54,74],"propose":[1],"a":[2,64],"branch-and-bound":[3],"framework":[4],"for":[5,11,86],"designing":[6,87],"non-reconfigurable":[7],"multiple":[8,38,56,88],"scan":[9,19,35,39,52,57,89],"chains":[10,58],"systems-on-chip":[12],"to":[13],"minimize":[14],"test":[15,60,80],"application":[16,61,81],"time.":[17],"Multiple":[18],"chain":[20],"design":[21,55],"problem":[22],"defined":[23],"in":[24,50,71,79],"this":[25],"paper":[26],"involves":[27],"(1)":[28],"partitioning":[29],"wrapper":[30,45],"cells":[31,46],"and":[32,41,47],"core":[33],"internal":[34],"registers":[36,49],"into":[37],"chains,":[40],"(2)":[42],"ordering":[43],"the":[44,48,68],"each":[51],"chain.":[53],"with":[59],"times":[62,82],"within":[63],"few":[65],"percentage":[66],"of":[67],"corresponding":[69],"optimal":[70],"practical":[72],"run-times.":[73],"also":[75],"demonstrate":[76],"significant":[77],"improvements":[78],"over":[83],"prior":[84],"heuristics":[85],"chains.":[90]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
