{"id":"https://openalex.org/W2004150203","doi":"https://doi.org/10.1109/ats.2003.1250843","title":"A BIST circuit for I/sub DDQ/ tests","display_name":"A BIST circuit for I/sub DDQ/ tests","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2004150203","doi":"https://doi.org/10.1109/ats.2003.1250843","mag":"2004150203"},"language":"en","primary_location":{"id":"doi:10.1109/ats.2003.1250843","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2003.1250843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2003 Test Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113950455","display_name":"Hashizume","orcid":null},"institutions":[{"id":"https://openalex.org/I922474255","display_name":"Tokushima University","ror":"https://ror.org/044vy1d05","country_code":"JP","type":"education","lineage":["https://openalex.org/I922474255"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hashizume","raw_affiliation_strings":["Tokushima Univ., Japan","Tokushima University, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokushima Univ., Japan","institution_ids":["https://openalex.org/I922474255"]},{"raw_affiliation_string":"Tokushima University, Japan","institution_ids":["https://openalex.org/I922474255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109345777","display_name":"\u300e Takeda","orcid":null},"institutions":[{"id":"https://openalex.org/I922474255","display_name":"Tokushima University","ror":"https://ror.org/044vy1d05","country_code":"JP","type":"education","lineage":["https://openalex.org/I922474255"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takeda","raw_affiliation_strings":["Tokushima Univ., Japan","Tokushima University, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokushima Univ., Japan","institution_ids":["https://openalex.org/I922474255"]},{"raw_affiliation_string":"Tokushima University, Japan","institution_ids":["https://openalex.org/I922474255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020250802","display_name":"Yotsuyanagi","orcid":null},"institutions":[{"id":"https://openalex.org/I922474255","display_name":"Tokushima University","ror":"https://ror.org/044vy1d05","country_code":"JP","type":"education","lineage":["https://openalex.org/I922474255"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yotsuyanagi","raw_affiliation_strings":["Tokushima Univ., Japan","Tokushima University, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokushima Univ., Japan","institution_ids":["https://openalex.org/I922474255"]},{"raw_affiliation_string":"Tokushima University, Japan","institution_ids":["https://openalex.org/I922474255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016417819","display_name":"Tamesada","orcid":null},"institutions":[{"id":"https://openalex.org/I922474255","display_name":"Tokushima University","ror":"https://ror.org/044vy1d05","country_code":"JP","type":"education","lineage":["https://openalex.org/I922474255"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tamesada","raw_affiliation_strings":["Tokushima Univ., Japan","Tokushima University, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokushima Univ., Japan","institution_ids":["https://openalex.org/I922474255"]},{"raw_affiliation_string":"Tokushima University, Japan","institution_ids":["https://openalex.org/I922474255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086680208","display_name":"Masatomo Miura","orcid":"https://orcid.org/0000-0001-7120-2425"},"institutions":[{"id":"https://openalex.org/I69740276","display_name":"Tokyo Metropolitan University","ror":"https://ror.org/00ws30h19","country_code":"JP","type":"education","lineage":["https://openalex.org/I69740276"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Miura","raw_affiliation_strings":["Tokyo Metropolitan University, Hachioji, Tokyo, Japan","Tokyo metropolitan Univ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Metropolitan University, Hachioji, Tokyo, Japan","institution_ids":["https://openalex.org/I69740276"]},{"raw_affiliation_string":"Tokyo metropolitan Univ","institution_ids":["https://openalex.org/I69740276"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110759533","display_name":"Kinoshita","orcid":null},"institutions":[{"id":"https://openalex.org/I11381156","display_name":"Osaka Gakuin University","ror":"https://ror.org/04a8t1e98","country_code":"JP","type":"education","lineage":["https://openalex.org/I11381156"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kinoshita","raw_affiliation_strings":["Osaka Gakuin University, Suita, Osaka, Japan","Osaka Gakuin University,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Osaka Gakuin University, Suita, Osaka, Japan","institution_ids":["https://openalex.org/I11381156"]},{"raw_affiliation_string":"Osaka Gakuin University,#TAB#","institution_ids":["https://openalex.org/I11381156"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12556138,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"390","last_page":"395"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.847366452217102},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6313146352767944},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6122763752937317},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5261456370353699},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5023055076599121},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4567524194717407},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45407426357269287},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3271285891532898},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.26737451553344727},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11296042799949646}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.847366452217102},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6313146352767944},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6122763752937317},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5261456370353699},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5023055076599121},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4567524194717407},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45407426357269287},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3271285891532898},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26737451553344727},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11296042799949646},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ats.2003.1250843","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2003.1250843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2003 Test Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.550000011920929,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1504336830","https://openalex.org/W1522828880","https://openalex.org/W1900735891","https://openalex.org/W1911194873","https://openalex.org/W2007826989","https://openalex.org/W2107511924","https://openalex.org/W2118058015","https://openalex.org/W2130958087","https://openalex.org/W2142925338","https://openalex.org/W2143645707","https://openalex.org/W2171392083","https://openalex.org/W2547476004","https://openalex.org/W6729604225"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W2096437374","https://openalex.org/W1943174035","https://openalex.org/W1928481607","https://openalex.org/W3135165657","https://openalex.org/W1485582195","https://openalex.org/W57337972","https://openalex.org/W2313216219","https://openalex.org/W2170979950","https://openalex.org/W2039299085"],"abstract_inverted_index":{"In":[0],"this":[1,67],"paper,":[2],"an":[3],"I/sub":[4,23,58],"DDQ/":[5,24,59],"test":[6,60,68],"time":[7,61],"reduction":[8],"method":[9],"is":[10,13,30,43,48],"proposed":[11],"which":[12],"suitable":[14],"for":[15,22],"BIST":[16,20,41],"approaches.":[17],"Also,":[18],"a":[19,35],"circuit":[21,38,42],"tests,":[25],"based":[26],"on":[27],"the":[28,40,46],"method,":[29],"proposed.":[31],"The":[32,53],"layout":[33],"of":[34],"CMOS":[36],"logic":[37],"having":[39],"designed":[44],"and":[45],"performance":[47],"evaluated":[49],"by":[50,65],"SPICE":[51],"simulation.":[52],"results":[54],"show":[55],"us":[56],"that":[57],"can":[62],"be":[63],"reduced":[64],"using":[66],"circuit.":[69]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
