{"id":"https://openalex.org/W1526682889","doi":"https://doi.org/10.1109/ats.2002.1181728","title":"A SoC test strategy based on a non-scan DFT method","display_name":"A SoC test strategy based on a non-scan DFT method","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W1526682889","doi":"https://doi.org/10.1109/ats.2002.1181728","mag":"1526682889"},"language":"en","primary_location":{"id":"doi:10.1109/ats.2002.1181728","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2002.1181728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071175870","display_name":"Hiroshi Date","orcid":"https://orcid.org/0000-0001-7262-6000"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"H. Date","raw_affiliation_strings":["Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":[]},{"raw_affiliation_string":"Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040112008","display_name":"T. Hosokawa","orcid":"https://orcid.org/0000-0001-7923-1781"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"T. Hosokawa","raw_affiliation_strings":["Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":[]},{"raw_affiliation_string":"Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113741180","display_name":"Michiaki Muraoka","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Muraoka","raw_affiliation_strings":["Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":[]},{"raw_affiliation_string":"Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"305","last_page":"310"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.787443995475769},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.734456479549408},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6194103360176086},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5971615314483643},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5658039450645447},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3378729224205017},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22138535976409912},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1529032588005066},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.10743662714958191},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.060411930084228516}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.787443995475769},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.734456479549408},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6194103360176086},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5971615314483643},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5658039450645447},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3378729224205017},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22138535976409912},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1529032588005066},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.10743662714958191},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.060411930084228516},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ats.2002.1181728","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2002.1181728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1483338234","https://openalex.org/W1554885925","https://openalex.org/W1837475237","https://openalex.org/W1855007419","https://openalex.org/W2054781056","https://openalex.org/W2098427313","https://openalex.org/W2113435641","https://openalex.org/W2131395796","https://openalex.org/W2155341318","https://openalex.org/W4302084786","https://openalex.org/W4302458519","https://openalex.org/W6633069435","https://openalex.org/W6664538138","https://openalex.org/W6674967428"],"related_works":["https://openalex.org/W4400235630","https://openalex.org/W1978339999","https://openalex.org/W2360400548","https://openalex.org/W2384601745","https://openalex.org/W2537171119","https://openalex.org/W2367495590","https://openalex.org/W2048370503","https://openalex.org/W2362119228","https://openalex.org/W2106258585","https://openalex.org/W2129632153"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,10,17,26],"system-on-a-chip":[4],"(SoC)":[5],"test":[6],"strategy":[7],"based":[8],"on":[9],"non-scan":[11],"DFT":[12,19,29],"method.":[13,30],"Especially,":[14],"we":[15],"evaluate":[16],"basic":[18],"method,":[20],"called":[21],"NS-DFT,":[22],"comparing":[23],"it":[24],"with":[25],"full":[27],"scan":[28],"The":[31],"experimental":[32],"results":[33],"for":[34],"practical":[35],"circuits":[36,39],"and":[37],"benchmark":[38],"demonstrate":[40],"the":[41,44],"efficiency":[42],"of":[43],"NS-DFT.":[45]},"counts_by_year":[],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}