{"id":"https://openalex.org/W7167635496","doi":"https://doi.org/10.1109/async69614.2026.00015","title":"A Test Architecture for Bundled-Data Asynchronous NoC Switches Using Commercial ATPG Tools","display_name":"A Test Architecture for Bundled-Data Asynchronous NoC Switches Using Commercial ATPG Tools","publication_year":2026,"publication_date":"2026-06-03","ids":{"openalex":"https://openalex.org/W7167635496","doi":"https://doi.org/10.1109/async69614.2026.00015"},"language":null,"primary_location":{"id":"doi:10.1109/async69614.2026.00015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async69614.2026.00015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 30th International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5121572090","display_name":"Iordana Gaisidou","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Iordana Gaisidou","raw_affiliation_strings":["University of Thessaly,Dep. of Electrical and Computer Engineering,Volos,Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Thessaly,Dep. of Electrical and Computer Engineering,Volos,Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5117839977","display_name":"Giuseppe Chessa","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Giuseppe Chessa","raw_affiliation_strings":["University of Manchester,Dep. of Computer Science,Manchester,UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Manchester,Dep. of Computer Science,Manchester,UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5135691698","display_name":"Giannis Giannoulas","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Giannis Giannoulas","raw_affiliation_strings":["University of Thessaly,Dep. of Electrical and Computer Engineering,Volos,Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Thessaly,Dep. of Electrical and Computer Engineering,Volos,Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059021602","display_name":"Artur Jutman","orcid":"https://orcid.org/0000-0002-2018-5589"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Artur Jutman","raw_affiliation_strings":["Tallinn University of Technology,Department of Computer Systems,Tallinn,Estonia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology,Department of Computer Systems,Tallinn,Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011268330","display_name":"Davide Bertozzi","orcid":"https://orcid.org/0000-0001-7462-4551"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Davide Bertozzi","raw_affiliation_strings":["University of Manchester,Dep. of Computer Science,Manchester,UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Manchester,Dep. of Computer Science,Manchester,UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5135670721","display_name":"Christos Sotiriou","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Christos Sotiriou","raw_affiliation_strings":["University of Thessaly,Dep. of Electrical and Computer Engineering,Volos,Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Thessaly,Dep. of Electrical and Computer Engineering,Volos,Greece","institution_ids":["https://openalex.org/I145722265"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"36","last_page":"44"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.489300012588501,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.489300012588501,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.2768000066280365,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.054099999368190765,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5691999793052673},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.49630001187324524},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.44279998540878296},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.41780000925064087},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.3028999865055084}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6166999936103821},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5691999793052673},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.49630001187324524},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48260000348091125},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.44279998540878296},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.41780000925064087},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4122999906539917},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.3028999865055084},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.2939000129699707},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2888000011444092},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.25290000438690186}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async69614.2026.00015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async69614.2026.00015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 30th International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320314731","display_name":"UK Research and Innovation","ror":"https://ror.org/001aqnf71"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1486202357","https://openalex.org/W1559109967","https://openalex.org/W1595368737","https://openalex.org/W1654782333","https://openalex.org/W1941043554","https://openalex.org/W2029279820","https://openalex.org/W2035720669","https://openalex.org/W2105231677","https://openalex.org/W2109020844","https://openalex.org/W2110259743","https://openalex.org/W2110477287","https://openalex.org/W2146606382","https://openalex.org/W2153120474","https://openalex.org/W2154699395","https://openalex.org/W2155694037","https://openalex.org/W2159951683","https://openalex.org/W2160214168","https://openalex.org/W2178247634","https://openalex.org/W2491977189","https://openalex.org/W2528284028","https://openalex.org/W2529211781","https://openalex.org/W2543533520","https://openalex.org/W2749476078","https://openalex.org/W2758064875","https://openalex.org/W2783525259","https://openalex.org/W2795404060","https://openalex.org/W2801441591","https://openalex.org/W2994825818","https://openalex.org/W3111684448","https://openalex.org/W3126000872","https://openalex.org/W3138783654","https://openalex.org/W3144514467","https://openalex.org/W4234698167","https://openalex.org/W4251474723","https://openalex.org/W4399013206","https://openalex.org/W4400977365"],"related_works":[],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2026-07-08T00:00:00"}