{"id":"https://openalex.org/W4386493494","doi":"https://doi.org/10.1109/async58294.2023.10239640","title":"Verification-Driven Design for Asynchronous VLSI","display_name":"Verification-Driven Design for Asynchronous VLSI","publication_year":2023,"publication_date":"2023-07-16","ids":{"openalex":"https://openalex.org/W4386493494","doi":"https://doi.org/10.1109/async58294.2023.10239640"},"language":"en","primary_location":{"id":"doi:10.1109/async58294.2023.10239640","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async58294.2023.10239640","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100389075","display_name":"Xiang Wu","orcid":"https://orcid.org/0000-0002-9642-8743"},"institutions":[{"id":"https://openalex.org/I32971472","display_name":"Yale University","ror":"https://ror.org/03v76x132","country_code":"US","type":"education","lineage":["https://openalex.org/I32971472"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiang Wu","raw_affiliation_strings":["Yale University,New Haven,CT,USA","Yale University, New Haven, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yale University,New Haven,CT,USA","institution_ids":["https://openalex.org/I32971472"]},{"raw_affiliation_string":"Yale University, New Haven, CT, USA","institution_ids":["https://openalex.org/I32971472"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002575415","display_name":"Rajit Manohar","orcid":"https://orcid.org/0000-0001-8211-6602"},"institutions":[{"id":"https://openalex.org/I32971472","display_name":"Yale University","ror":"https://ror.org/03v76x132","country_code":"US","type":"education","lineage":["https://openalex.org/I32971472"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajit Manohar","raw_affiliation_strings":["Yale University,New Haven,CT,USA","Yale University, New Haven, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yale University,New Haven,CT,USA","institution_ids":["https://openalex.org/I32971472"]},{"raw_affiliation_string":"Yale University, New Haven, CT, USA","institution_ids":["https://openalex.org/I32971472"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I32971472"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"78","last_page":"88"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8454979658126831},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6465892195701599},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.5905038714408875},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5524151921272278},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5435923337936401},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.5410839319229126},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5355111956596375},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5294468402862549},{"id":"https://openalex.org/keywords/rewriting","display_name":"Rewriting","score":0.5127032995223999},{"id":"https://openalex.org/keywords/software-verification","display_name":"Software verification","score":0.4633598327636719},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4439617693424225},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.4296417832374573},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4175122082233429},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4110402464866638},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38271963596343994},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33036190271377563},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3005416691303253},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.22087520360946655},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.17789945006370544}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8454979658126831},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6465892195701599},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5905038714408875},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5524151921272278},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5435923337936401},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.5410839319229126},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5355111956596375},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5294468402862549},{"id":"https://openalex.org/C154690210","wikidata":"https://www.wikidata.org/wiki/Q1668499","display_name":"Rewriting","level":2,"score":0.5127032995223999},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.4633598327636719},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4439617693424225},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.4296417832374573},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4175122082233429},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4110402464866638},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38271963596343994},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33036190271377563},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3005416691303253},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.22087520360946655},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.17789945006370544},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async58294.2023.10239640","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async58294.2023.10239640","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":47,"referenced_works":["https://openalex.org/W123132062","https://openalex.org/W1480909796","https://openalex.org/W1487199072","https://openalex.org/W1490084794","https://openalex.org/W1491178396","https://openalex.org/W1741528175","https://openalex.org/W1882160752","https://openalex.org/W2003164052","https://openalex.org/W2016449454","https://openalex.org/W2029005287","https://openalex.org/W2041152728","https://openalex.org/W2057843078","https://openalex.org/W2064422880","https://openalex.org/W2066210260","https://openalex.org/W2076667206","https://openalex.org/W2078250023","https://openalex.org/W2081591620","https://openalex.org/W2091302783","https://openalex.org/W2103953153","https://openalex.org/W2104105510","https://openalex.org/W2107995193","https://openalex.org/W2127637733","https://openalex.org/W2134087751","https://openalex.org/W2137308459","https://openalex.org/W2137351629","https://openalex.org/W2139151574","https://openalex.org/W2148817888","https://openalex.org/W2154701980","https://openalex.org/W2155327371","https://openalex.org/W2156956883","https://openalex.org/W2169991924","https://openalex.org/W2171318521","https://openalex.org/W2753285289","https://openalex.org/W2906795935","https://openalex.org/W2911450990","https://openalex.org/W2979142728","https://openalex.org/W3011481298","https://openalex.org/W3033189783","https://openalex.org/W3121710465","https://openalex.org/W3206261744","https://openalex.org/W4211008702","https://openalex.org/W6605069955","https://openalex.org/W6629214762","https://openalex.org/W6629325410","https://openalex.org/W6675350323","https://openalex.org/W6684957772","https://openalex.org/W6757947563"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2392047570","https://openalex.org/W2363848262","https://openalex.org/W2355428260","https://openalex.org/W3036403349","https://openalex.org/W1985271980","https://openalex.org/W2059150015","https://openalex.org/W3155012083","https://openalex.org/W2035244079","https://openalex.org/W2962898432"],"abstract_inverted_index":{"Although":[0],"verification":[1],"has":[2],"widespread":[3],"use":[4],"in":[5,13,41,60,72,149],"hardware":[6,19,52,54,106],"design,":[7],"there":[8],"is":[9,77,120,135],"still":[10],"a":[11,61,70,88,98,123,138],"gap":[12],"verifying":[14],"the":[15,46,110,144],"functional":[16,91],"description":[17,92],"of":[18,48,105],"against":[20],"its":[21],"detailed":[22],"design.":[23],"In":[24],"this":[25,66,150],"paper,":[26],"we":[27,44],"present":[28],"our":[29,130],"effort":[30],"to":[31,79,100,137],"close":[32],"that":[33,76,129],"gap.":[34],"Drawing":[35],"an":[36],"analogy":[37],"from":[38,87],"test-driven":[39],"development":[40],"software":[42,80,116],"development,":[43],"propose":[45,97],"idea":[47,67],"verification-driven":[49],"design":[50,55,75,134],"for":[51,115],"design\u2014the":[53],"flow":[56],"should":[57],"be":[58],"engineered":[59],"verification-friendly":[62],"way.":[63],"We":[64,96,127],"showcase":[65],"by":[68,108,122],"leveraging":[69],"methodology":[71],"asynchronous":[73],"circuit":[74],"similar":[78],"optimization\u2014complicated,":[81],"parallel":[82,131],"microarchitectural":[83],"optimizations":[84],"are":[85],"derived":[86],"simple,":[89],"sequential":[90,139],"through":[93],"iterative":[94],"rewriting.":[95],"technique":[99,147],"formally":[101],"verify":[102],"these":[103],"transformations":[104],"designs":[107],"extending":[109],"state-of-the-art":[111],"translation":[112,145],"validation":[113,146],"algorithm":[114],"verification.":[117],"This":[118],"approach":[119],"demonstrated":[121],"superscalar":[124,132],"processor":[125,133,141],"example.":[126],"assert":[128],"equivalent":[136],"non-superscalar":[140],"specification":[142],"using":[143],"presented":[148],"paper.":[151]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}