{"id":"https://openalex.org/W4386486481","doi":"https://doi.org/10.1109/async58294.2023.10239616","title":"Designing Self-timed Asynchronous Circuits with Chisel","display_name":"Designing Self-timed Asynchronous Circuits with Chisel","publication_year":2023,"publication_date":"2023-07-16","ids":{"openalex":"https://openalex.org/W4386486481","doi":"https://doi.org/10.1109/async58294.2023.10239616"},"language":"en","primary_location":{"id":"doi:10.1109/async58294.2023.10239616","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async58294.2023.10239616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100624320","display_name":"Jilin Zhang","orcid":"https://orcid.org/0000-0002-0423-9356"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jilin Zhang","raw_affiliation_strings":["Tsinghua University,School of Integrated Circuits,Beijing,China","School of Integrated Circuits, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"School of Integrated Circuits, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074747392","display_name":"Chunqi Qian","orcid":"https://orcid.org/0000-0003-4528-4572"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chunqi Qian","raw_affiliation_strings":["Tsinghua University,School of Integrated Circuits,Beijing,China","School of Integrated Circuits, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"School of Integrated Circuits, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088276807","display_name":"Dexuan Huo","orcid":"https://orcid.org/0000-0002-0452-3998"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dexuan Huo","raw_affiliation_strings":["Tsinghua University,School of Integrated Circuits,Beijing,China","School of Integrated Circuits, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"School of Integrated Circuits, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100410088","display_name":"Jian Zhang","orcid":"https://orcid.org/0000-0003-3822-2533"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Zhang","raw_affiliation_strings":["Tsinghua University,School of Integrated Circuits,Beijing,China","School of Integrated Circuits, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"School of Integrated Circuits, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100420459","display_name":"Hong Chen","orcid":"https://orcid.org/0000-0003-0774-1410"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hong Chen","raw_affiliation_strings":["Tsinghua University,School of Integrated Circuits,Beijing,China","School of Integrated Circuits, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"School of Integrated Circuits, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100624320"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.4016,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.6035142,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"27","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8009597063064575},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.6618951559066772},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5644436478614807},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5139681696891785},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4570576846599579},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4565117359161377},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4307246208190918},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41869041323661804},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3715643286705017},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3537876605987549},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33358335494995117},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.33142969012260437}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8009597063064575},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.6618951559066772},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5644436478614807},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5139681696891785},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4570576846599579},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4565117359161377},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4307246208190918},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41869041323661804},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3715643286705017},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3537876605987549},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33358335494995117},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.33142969012260437},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async58294.2023.10239616","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async58294.2023.10239616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320329860","display_name":"National Science and Technology Major Project","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1983394510","https://openalex.org/W2071429830","https://openalex.org/W2798580280","https://openalex.org/W2800632527","https://openalex.org/W2885909075","https://openalex.org/W2907520127","https://openalex.org/W2978614371","https://openalex.org/W2982447857","https://openalex.org/W3103997615","https://openalex.org/W3128516589","https://openalex.org/W3134635013","https://openalex.org/W3210378525","https://openalex.org/W3212113734","https://openalex.org/W4240172596","https://openalex.org/W4310454550"],"related_works":["https://openalex.org/W2170314243","https://openalex.org/W2119179026","https://openalex.org/W2794947590","https://openalex.org/W2129508730","https://openalex.org/W2004826944","https://openalex.org/W2372022246","https://openalex.org/W2544421437","https://openalex.org/W1935030095","https://openalex.org/W2111408175","https://openalex.org/W2326497555"],"abstract_inverted_index":{"As":[0],"an":[1,107,180],"embedded":[2],"library":[3,52],"of":[4,13,72,93,142,175],"the":[5,70,99,103,111,116,120,129,140,147,199],"Scala":[6],"programming":[7],"language":[8,25],"that":[9,166],"leverages":[10],"many":[11],"features":[12],"object-oriented":[14],"and":[15,90,124,149,156,186],"functional":[16],"programming,":[17],"Chisel":[18,77,89,104,185],"is":[19,53,78,132],"a":[20,33,49,91,190],"new":[21],"generation":[22],"hardware":[23],"construction":[24],"designed":[26,75],"for":[27,36,66],"agile":[28],"development.":[29],"This":[30],"paper":[31],"proposes":[32],"design":[34,131,179],"flow":[35],"designing":[37],"self-timed":[38],"asynchronous":[39,51,64,73,95,100,181],"circuits":[40,74,153],"using":[41,184],"Chisel,":[42,57],"which":[43,58],"has":[44],"two":[45],"main":[46],"features:":[47],"1)":[48],"reusable":[50,94],"created":[54],"based":[55],"on":[56,154],"allows":[59],"designers":[60,87],"to":[61,97,118,194],"develop":[62],"flexible":[63],"modules":[65],"different":[67],"applications;":[68],"2)":[69],"analysis":[71],"with":[76,134,159,162,189],"automatic,":[79],"including":[80],"auto-timing":[81],"constraints":[82],"generation.":[83],"In":[84],"our":[85,143,196],"flow,":[86],"use":[88],"set":[92],"libraries":[96],"describe":[98],"circuit.":[101],"Then,":[102],"compiler":[105],"generates":[106],"intermediate":[108],"representation.":[109],"Next,":[110],"circuit":[112],"transformation":[113],"module":[114],"analyzes":[115],"IR":[117],"generate":[119],"final":[121],"Verilog":[122],"netlist":[123],"timing":[125],"constraint":[126],"files.":[127],"Finally,":[128],"backend":[130],"realized":[133],"commercial":[135],"EDA":[136],"tools.":[137],"To":[138],"demonstrate":[139],"feasibility":[141],"approach,":[144],"we":[145,178],"implement":[146,187],"Fibonacci":[148],"greatest":[150],"common":[151],"divisor":[152],"FPGA":[155],"compare":[157],"them":[158],"previous":[160],"designs":[161,168],"VHDL.":[163],"We":[164],"find":[165],"Chisel-based":[167],"have":[169],"at":[170],"least":[171],"70%":[172],"fewer":[173],"lines":[174],"code.":[176],"Besides,":[177],"SNN":[182],"processor(ANP-T)":[183],"it":[188],"22nm":[191],"CMOS":[192],"process":[193],"verify":[195],"approach":[197],"in":[198],"ASIC":[200],"flow.":[201]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
