{"id":"https://openalex.org/W3082610577","doi":"https://doi.org/10.1109/async49171.2020.00008","title":"Timing Errors in STA-based Gate-Level Simulation","display_name":"Timing Errors in STA-based Gate-Level Simulation","publication_year":2020,"publication_date":"2020-05-01","ids":{"openalex":"https://openalex.org/W3082610577","doi":"https://doi.org/10.1109/async49171.2020.00008","mag":"3082610577"},"language":"en","primary_location":{"id":"doi:10.1109/async49171.2020.00008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async49171.2020.00008","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057901469","display_name":"Stavros Simoglou","orcid":"https://orcid.org/0000-0003-0015-7510"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Stavros Simoglou","raw_affiliation_strings":["EECE Department, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"EECE Department, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103066371","display_name":"Christos Sotiriou","orcid":"https://orcid.org/0000-0001-9318-474X"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Christos Sotiriou","raw_affiliation_strings":["EECE Department, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"EECE Department, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063643730","display_name":"Nikolaos Blias","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nikolaos Blias","raw_affiliation_strings":["EECE Department, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"EECE Department, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5057901469"],"corresponding_institution_ids":["https://openalex.org/I145722265"],"apc_list":null,"apc_paid":null,"fwci":0.1037,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.43075184,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.9067639708518982},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6542061567306519},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6087444424629211},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5097953677177429},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5075362920761108},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5063296556472778},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47984787821769714},{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.4585864245891571},{"id":"https://openalex.org/keywords/bounded-function","display_name":"Bounded function","score":0.44569164514541626},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4379880726337433},{"id":"https://openalex.org/keywords/transistor-model","display_name":"Transistor model","score":0.42593562602996826},{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.42545953392982483},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33036720752716064},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2531849145889282},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2065896987915039},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19524651765823364},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17743560671806335},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13541966676712036},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08909589052200317}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.9067639708518982},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6542061567306519},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6087444424629211},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5097953677177429},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5075362920761108},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5063296556472778},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47984787821769714},{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.4585864245891571},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.44569164514541626},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4379880726337433},{"id":"https://openalex.org/C150169584","wikidata":"https://www.wikidata.org/wiki/Q7834319","display_name":"Transistor model","level":4,"score":0.42593562602996826},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.42545953392982483},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33036720752716064},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2531849145889282},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2065896987915039},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19524651765823364},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17743560671806335},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13541966676712036},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08909589052200317},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/async49171.2020.00008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async49171.2020.00008","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"},{"id":"pmh:oai:ir.lib.uth.gr:11615/78987","is_oa":false,"landing_page_url":"http://hdl.handle.net/11615/78987","pdf_url":null,"source":{"id":"https://openalex.org/S4306400243","display_name":"University of Thessaly Institutional Repository (University of Thessaly)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I145722265","host_organization_name":"University of Thessaly","host_organization_lineage":["https://openalex.org/I145722265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - International Symposium on Asynchronous Circuits and Systems","raw_type":"conferenceItem"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1829133288","https://openalex.org/W2160823654","https://openalex.org/W2607359301","https://openalex.org/W2914903263","https://openalex.org/W2979377739","https://openalex.org/W3047136511","https://openalex.org/W6638744798"],"related_works":["https://openalex.org/W2797744477","https://openalex.org/W2018560541","https://openalex.org/W4234364140","https://openalex.org/W1986847619","https://openalex.org/W4229446324","https://openalex.org/W2118902095","https://openalex.org/W1972185800","https://openalex.org/W2107551409","https://openalex.org/W1968332896","https://openalex.org/W4249541960"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"demonstrate":[4,103],"that":[5],"conventional":[6],"STA-based,":[7],"functional,":[8],"gate-level":[9,94],"simulation":[10,95],"of":[11,56,106],"asynchronous":[12],"circuits":[13],"with":[14,97],"cycles":[15,70],"is":[16,71],"only":[17],"as":[18,20,79],"accurate":[19],"the":[21,51,104],"STA":[22,90],"engine":[23],"used.":[24],"This":[25],"is,":[26],"firstly":[27],"because":[28,39],"cycle":[29],"cuts":[30],"create":[31],"local":[32],"slew":[33,40],"errors":[34],"at":[35],"cutpoints,":[36],"and":[37,65,91,102],"secondly":[38],"propagation":[41],"may":[42],"not":[43,62],"be":[44],"upper-bounded":[45],"across":[46,69],"multiple":[47],"cut":[48,63],"points":[49],"in":[50],"same":[52],"cycle.":[53],"The":[54],"use":[55],"an":[57,80],"ASTA":[58],"engine,":[59],"which":[60,75],"does":[61],"cycles,":[64],"properly":[66],"bounds":[67],"slews":[68],"a":[72],"possible":[73],"solution,":[74],"can":[76],"indeed":[77],"serve":[78],"upper":[81],"bound":[82],"over":[83],"SPICE,":[84],"transistor":[85,98],"level":[86,99],"similations.":[87],"We":[88],"contrast":[89],"ASTA-based":[92],"SDF-annotated":[93],"results,":[96,101],"SPICE":[100],"impact":[105],"timing":[107],"errors.":[108]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2020-09-08T00:00:00"}
