{"id":"https://openalex.org/W2154658572","doi":"https://doi.org/10.1109/async.2007.7","title":"A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability","display_name":"A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W2154658572","doi":"https://doi.org/10.1109/async.2007.7","mag":"2154658572"},"language":"en","primary_location":{"id":"doi:10.1109/async.2007.7","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2007.7","pdf_url":null,"source":{"id":"https://openalex.org/S4210190146","display_name":"Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems","issn_l":"1522-8681","issn":["1522-8681"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026091296","display_name":"Nikolaos Minas","orcid":null},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Nikolaos Minas","raw_affiliation_strings":["University of Newcastle, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109215825","display_name":"D.J. Kinniment","orcid":null},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David Kinniment","raw_affiliation_strings":["University of Newcastle, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111970447","display_name":"Keith Heron","orcid":null},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Keith Heron","raw_affiliation_strings":["University of Newcastle, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102155222","display_name":"Gordon Russell","orcid":null},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Gordon Russell","raw_affiliation_strings":["University of Newcastle, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I84884186"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"163","last_page":"174"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9912999868392944,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7470890879631042},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6826962232589722},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.6773868799209595},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6248346567153931},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6016310453414917},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.5320070385932922},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.47088250517845154},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47012078762054443},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4633648097515106},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45302245020866394},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3722684979438782},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3450906276702881},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19524937868118286},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.19107741117477417},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14798858761787415},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.12377545237541199},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11213943362236023}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7470890879631042},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6826962232589722},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.6773868799209595},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6248346567153931},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6016310453414917},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.5320070385932922},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.47088250517845154},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47012078762054443},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4633648097515106},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45302245020866394},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3722684979438782},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3450906276702881},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19524937868118286},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.19107741117477417},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14798858761787415},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.12377545237541199},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11213943362236023},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.2007.7","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2007.7","pdf_url":null,"source":{"id":"https://openalex.org/S4210190146","display_name":"Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems","issn_l":"1522-8681","issn":["1522-8681"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5799999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1666015432","https://openalex.org/W1967575124","https://openalex.org/W1973902586","https://openalex.org/W2062952706","https://openalex.org/W2074853895","https://openalex.org/W2118358623","https://openalex.org/W2118803820","https://openalex.org/W2147196983","https://openalex.org/W2152443753","https://openalex.org/W2160450711","https://openalex.org/W2166277301","https://openalex.org/W3100011130","https://openalex.org/W3142526730","https://openalex.org/W4232143692"],"related_works":["https://openalex.org/W2369836424","https://openalex.org/W2901028619","https://openalex.org/W2362706271","https://openalex.org/W2831860248","https://openalex.org/W3195700791","https://openalex.org/W2905193124","https://openalex.org/W2361615631","https://openalex.org/W2790282971","https://openalex.org/W2904912720","https://openalex.org/W2059944403"],"abstract_inverted_index":{"Timing":[0],"issues":[1],"are":[2],"a":[3,76,128],"major":[4],"concern":[5],"in":[6,116],"the":[7,19,37,40,45,55,91,98,114,121],"design":[8],"of":[9,21,39,47,57,93,108,124,127],"high":[10],"performance":[11],"synchronous,":[12],"asynchronous":[13],"circuits":[14],"and":[15],"GALS.":[16],"Investigations":[17],"into":[18],"causes":[20],"many":[22],"timing":[23,59],"problems":[24],"cannot":[25],"be":[26],"satisfactorily":[27],"undertaken":[28],"using":[29],"external":[30],"equipment":[31],"due":[32],"to":[33,62,79,89,102],"its":[34],"remoteness":[35],"from":[36],"source":[38],"potential":[41],"problem;":[42],"this":[43],"necessitates":[44],"development":[46],"on-chip":[48,85],"time":[49,99],"measurement":[50],"circuitry.":[51],"Current":[52],"techniques":[53,115],"have":[54],"capability":[56],"resolving":[58],"differences":[60],"down":[61,101],"5ps":[63],"[1],":[64],"however":[65],"further":[66],"improvement":[67],"is":[68,105,110],"impeded":[69],"by":[70,112],"process":[71,94],"variations.":[72],"This":[73],"paper":[74],"describes":[75],"flash":[77],"Time":[78],"Digital":[80],"Converter":[81],"(TDC)":[82],"suitable":[83],"for":[84],"implementation.":[86],"The":[87],"theory":[88],"overcome":[90],"effects":[92],"variations,":[95],"potentially":[96],"permitting":[97],"resolution":[100,123],"one":[103],"picosecond":[104],"described.":[106],"Proof":[107],"concept":[109],"demonstrated":[111],"implementing":[113],"an":[117],"FPGA,":[118],"improving":[119],"on":[120],"current":[122],"FPGA":[125],"implementation":[126],"TDC.":[129]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
