{"id":"https://openalex.org/W2100917017","doi":"https://doi.org/10.1109/async.2007.17","title":"Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication","display_name":"Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W2100917017","doi":"https://doi.org/10.1109/async.2007.17","mag":"2100917017"},"language":"en","primary_location":{"id":"doi:10.1109/async.2007.17","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2007.17","pdf_url":null,"source":{"id":"https://openalex.org/S4210190146","display_name":"Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems","issn_l":"1522-8681","issn":["1522-8681"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110038076","display_name":"Amitava Mitra","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Amitava Mitra","raw_affiliation_strings":["Intel Corporation, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010343450","display_name":"William McLaughlin","orcid":null},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"William F. McLaughlin","raw_affiliation_strings":["Department of Electrical Engineering, Columbia University, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Columbia University, USA","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023548648","display_name":"Steven M. Nowick","orcid":"https://orcid.org/0000-0002-8837-8109"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven M. Nowick","raw_affiliation_strings":["Department of Computer Science, Columbia University, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Columbia University, USA","institution_ids":["https://openalex.org/I78577930"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110038076"],"corresponding_institution_ids":["https://openalex.org/I4210146682"],"apc_list":null,"apc_paid":null,"fwci":3.1612,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.91615834,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"186","last_page":"195"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7874388694763184},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7508541941642761},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.5672959685325623},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5186100006103516},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5157580375671387},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4576110243797302},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4388645887374878},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.42834246158599854},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37583667039871216},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3421139717102051},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.328067421913147},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.25512832403182983},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21384543180465698},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1383139193058014},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10833552479743958},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10702303051948547},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08098021149635315}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7874388694763184},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7508541941642761},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.5672959685325623},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5186100006103516},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5157580375671387},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4576110243797302},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4388645887374878},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.42834246158599854},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37583667039871216},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3421139717102051},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.328067421913147},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.25512832403182983},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21384543180465698},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1383139193058014},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10833552479743958},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10702303051948547},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08098021149635315},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.2007.17","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2007.17","pdf_url":null,"source":{"id":"https://openalex.org/S4210190146","display_name":"Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems","issn_l":"1522-8681","issn":["1522-8681"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1769133684","https://openalex.org/W2086743684","https://openalex.org/W2104610013","https://openalex.org/W2112431253","https://openalex.org/W2143626656","https://openalex.org/W2157179403","https://openalex.org/W2157617940","https://openalex.org/W2160776998","https://openalex.org/W6638190992"],"related_works":["https://openalex.org/W631083485","https://openalex.org/W4313452936","https://openalex.org/W2097026685","https://openalex.org/W2116677773","https://openalex.org/W2480068220","https://openalex.org/W2070883797","https://openalex.org/W4386859288","https://openalex.org/W2102542442","https://openalex.org/W1986220761","https://openalex.org/W2042495646"],"abstract_inverted_index":{"As":[0],"system-level":[1,32],"interconnect":[2],"incurs":[3],"increasing":[4,18],"penalties":[5],"in":[6,25,35,166],"latency,":[7],"round-trip":[8],"cycle":[9],"time":[10],"and":[11,13,66,81,93,111,139,159],"power,":[12],"as":[14,136,183,185],"timing-variability":[15],"becomes":[16],"an":[17,186],"design":[19,87],"challenge,":[20],"there":[21],"is":[22,42,100],"renewed":[23],"interest":[24],"using":[26],"two-phase":[27,51,91,106],"delay-insensitive":[28],"protocols":[29,92],"for":[30,69,108,117],"global":[31,90,109],"communication.":[33],"However,":[34,121],"practice,":[36],"when":[37],"designing":[38],"asynchronous":[39,73,118],"systems,":[40],"it":[41],"extremely":[43],"inefficient":[44],"to":[45,129],"build":[46],"local":[47,94],"computation":[48,55,119,178,188],"nodes":[49],"with":[50,88,122,148],"logic,":[52],"hence":[53],"four-phase":[54,82,95,113,133],"blocks":[56],"are":[57,127,145,172],"typically":[58],"used.":[59],"This":[60],"paper":[61],"proposes":[62],"a":[63,70,102,112,167,176],"new":[64],"architecture,":[65],"circuit-level":[67],"implementations,":[68,154],"family":[71],"of":[72],"protocol":[74,107,116],"converters,":[75],"which":[76],"efficiently":[77],"convert":[78],"between":[79],"two-":[80],"protocols,":[83,134],"thus":[84],"facilitating":[85],"system":[86],"robust":[89],"protocols.":[96],"The":[97,143],"main":[98],"focus":[99],"on":[101],"level-encoded":[103],"dual-rail":[104],"(LEDR)":[105],"communication,":[110],"return-to-zero":[114],"(RZ)":[115],"blocks.":[120],"small":[123,177],"modifications,":[124],"the":[125],"converters":[126,144],"extended":[128],"handle":[130],"other":[131],"common":[132],"such":[135],"1-":[137],"of-4":[138],"single-rail":[140],"bundled":[141],"data.":[142],"highly":[146],"robust,":[147],"almost":[149],"entirely":[150],"quasi":[151],"delay-":[152],"insensitive":[153],"yet":[155],"exhibit":[156],"high":[157],"performance":[158],"modest":[160],"area":[161],"overhead.":[162],"Initial":[163],"post-layout":[164],"simulations":[165],"0.18":[168],"micron":[169],"TSMC":[170],"process":[171],"provided,":[173],"both":[174],"assuming":[175],"block":[179,189],"(8times8":[180],"combinational":[181],"multiplier)":[182],"well":[184],"empty":[187],"(FIFO":[190],"stage).":[191]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}