{"id":"https://openalex.org/W2139349254","doi":"https://doi.org/10.1109/async.2007.15","title":"Demystifying Data-Driven and Pausible Clocking Schemes","display_name":"Demystifying Data-Driven and Pausible Clocking Schemes","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W2139349254","doi":"https://doi.org/10.1109/async.2007.15","mag":"2139349254"},"language":"en","primary_location":{"id":"doi:10.1109/async.2007.15","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2007.15","pdf_url":null,"source":{"id":"https://openalex.org/S4210190146","display_name":"Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems","issn_l":"1522-8681","issn":["1522-8681"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040762162","display_name":"Robert Mullins","orcid":"https://orcid.org/0000-0002-8393-2748"},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Robert Mullins","raw_affiliation_strings":["Computer Laboratory, University of Cambridge, UK","Comput. Lab. Univ. of Cambridge, Cambridge"],"affiliations":[{"raw_affiliation_string":"Computer Laboratory, University of Cambridge, UK","institution_ids":["https://openalex.org/I241749"]},{"raw_affiliation_string":"Comput. Lab. Univ. of Cambridge, Cambridge","institution_ids":["https://openalex.org/I241749"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041439799","display_name":"Simon W. Moore","orcid":"https://orcid.org/0000-0002-2806-495X"},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Simon Moore","raw_affiliation_strings":["Computer Laboratory, University of Cambridge, UK","Comput. Lab. Univ. of Cambridge, Cambridge"],"affiliations":[{"raw_affiliation_string":"Computer Laboratory, University of Cambridge, UK","institution_ids":["https://openalex.org/I241749"]},{"raw_affiliation_string":"Comput. Lab. Univ. of Cambridge, Cambridge","institution_ids":["https://openalex.org/I241749"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5040762162"],"corresponding_institution_ids":["https://openalex.org/I241749"],"apc_list":null,"apc_paid":null,"fwci":8.4298,"has_fulltext":false,"cited_by_count":61,"citation_normalized_percentile":{"value":0.97919762,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"175","last_page":"185"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6768535375595093}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6768535375595093}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.2007.15","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2007.15","pdf_url":null,"source":{"id":"https://openalex.org/S4210190146","display_name":"Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems","issn_l":"1522-8681","issn":["1522-8681"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","score":0.7900000214576721,"id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W158833317","https://openalex.org/W1496179771","https://openalex.org/W1609287256","https://openalex.org/W1971600474","https://openalex.org/W2005345974","https://openalex.org/W2012155933","https://openalex.org/W2033045135","https://openalex.org/W2043318181","https://openalex.org/W2063306466","https://openalex.org/W2085950572","https://openalex.org/W2098996548","https://openalex.org/W2102639604","https://openalex.org/W2108085346","https://openalex.org/W2113936155","https://openalex.org/W2114453311","https://openalex.org/W2116651175","https://openalex.org/W2120480196","https://openalex.org/W2127444466","https://openalex.org/W2131781655","https://openalex.org/W2132700530","https://openalex.org/W2134157563","https://openalex.org/W2134425298","https://openalex.org/W2146587443","https://openalex.org/W2147082276","https://openalex.org/W2150415477","https://openalex.org/W2150872535","https://openalex.org/W2154636015","https://openalex.org/W2165370369","https://openalex.org/W2168916081","https://openalex.org/W2296054660","https://openalex.org/W2487142227","https://openalex.org/W2495832856","https://openalex.org/W2541217642","https://openalex.org/W2911717499","https://openalex.org/W4230776322","https://openalex.org/W4231905827","https://openalex.org/W4234807381","https://openalex.org/W6642908052","https://openalex.org/W6651790823"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2478288626","https://openalex.org/W4391913857","https://openalex.org/W2350741829","https://openalex.org/W2530322880"],"abstract_inverted_index":{"VLSI":[0],"systems":[1,136],"are":[2,97],"often":[3,98],"constructed":[4],"from":[5],"a":[6,16],"multitude":[7],"of":[8,35,85,121,128],"independently":[9],"clocked":[10],"synchronous":[11,17,40,135],"IP":[12],"blocks.":[13],"Unfortunately,":[14],"while":[15],"design":[18],"style":[19],"may":[20],"produce":[21],"efficient":[22],"block":[23,41],"level":[24],"implementations":[25,113],"it":[26],"does":[27],"little":[28],"to":[29,38,45,55,61,117,132,137],"support":[30],"their":[31,49],"composition.":[32],"The":[33,125],"addition":[34],"asynchronous":[36],"interfaces":[37,52],"each":[39],"is":[42,131],"one":[43],"way":[44],"simplify":[46],"and":[47,69,77,114,142],"strengthen":[48],"integration.":[50],"Asynchronous":[51],"allow":[53],"blocks":[54],"be":[56,138],"composed":[57,139],"without":[58],"the":[59,82,119],"need":[60],"consider":[62],"synchronisation":[63],"failure":[64],"rates,":[65],"permit":[66,133],"data-driven":[67],"operation":[68],"provide":[70,115],"greater":[71],"freedom":[72],"when":[73],"designing":[74],"on-chip":[75],"buses":[76],"networks.":[78],"This":[79],"paper":[80],"surveys":[81],"significant":[83],"body":[84],"published":[86],"work":[87,130],"in":[88,102],"this":[89,129],"area.":[90],"We":[91,107],"highlight":[92],"similarities":[93],"between":[94],"schemes":[95],"that":[96],"concealed":[99],"by":[100],"differences":[101],"specification":[103],"or":[104],"circuit":[105],"style.":[106],"also":[108],"present":[109],"new":[110],"local":[111],"clock":[112],"solutions":[116],"mitigate":[118],"effect":[120],"clock-tree":[122],"insertion":[123],"delays.":[124],"ultimate":[126],"goal":[127],"multi-clock":[134],"simply,":[140],"robustly":[141],"efficiently.":[143]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}