{"id":"https://openalex.org/W1934130410","doi":"https://doi.org/10.1109/async.2004.1299297","title":"Hiding synchronization delays in a GALS processor microarchitecture","display_name":"Hiding synchronization delays in a GALS processor microarchitecture","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W1934130410","doi":"https://doi.org/10.1109/async.2004.1299297","mag":"1934130410"},"language":"en","primary_location":{"id":"doi:10.1109/async.2004.1299297","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2004.1299297","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/97036","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066524934","display_name":"G. Semeraro","orcid":null},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Semeraro","raw_affiliation_strings":["Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA","Department of Computer Engineering, Rochester Institute of Technology, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA","institution_ids":["https://openalex.org/I155173764"]},{"raw_affiliation_string":"Department of Computer Engineering, Rochester Institute of Technology, USA#TAB#","institution_ids":["https://openalex.org/I155173764"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009386140","display_name":"David H. Albonesi","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.H. Albonesi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000686736","display_name":"Grigorios Magklis","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Magklis","raw_affiliation_strings":["Department of Computer Science, University of Rochester, Rochester, NY, USA","Dept. of Computer Science, University of Rochester, Rochester, NY, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"Dept. of Computer Science, University of Rochester, Rochester, NY, USA#TAB#","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079254515","display_name":"Michael L. Scott","orcid":"https://orcid.org/0000-0001-8652-7644"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.L. Scott","raw_affiliation_strings":["Department of Computer Science, University of Rochester, Rochester, NY, USA","Dept. of Computer Science, University of Rochester, Rochester, NY, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"Dept. of Computer Science, University of Rochester, Rochester, NY, USA#TAB#","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113685821","display_name":"S. Dropsho","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.G. Dropsho","raw_affiliation_strings":["Department of Computer Science, University of Rochester, Rochester, NY, USA","Dept. of Computer Science, University of Rochester, Rochester, NY, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"Dept. of Computer Science, University of Rochester, Rochester, NY, USA#TAB#","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013232946","display_name":"Sandhya Dwarkadas","orcid":"https://orcid.org/0000-0003-2631-8191"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Dwarkadas","raw_affiliation_strings":["Department of Computer Science, University of Rochester, Rochester, NY, USA","Dept. of Computer Science, University of Rochester, Rochester, NY, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"Dept. of Computer Science, University of Rochester, Rochester, NY, USA#TAB#","institution_ids":["https://openalex.org/I5388228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"159","last_page":"169"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.8900622725486755},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8330351114273071},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7326764464378357},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6959724426269531},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.635691225528717},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.5850149989128113},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5464692115783691},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.528508722782135},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4984111785888672},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.43035799264907837},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.4294326603412628},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3214687407016754},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.08545157313346863},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.0845535397529602}],"concepts":[{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.8900622725486755},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8330351114273071},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7326764464378357},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6959724426269531},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.635691225528717},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.5850149989128113},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5464692115783691},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.528508722782135},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4984111785888672},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.43035799264907837},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.4294326603412628},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3214687407016754},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.08545157313346863},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0845535397529602},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/async.2004.1299297","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2004.1299297","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.380.6209","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.380.6209","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ftp.cs.rochester.edu/u/scott/papers/2004_Async.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.91.3464","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.3464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.rochester.edu/~maglis/ftp/semeraro_async04.pdf","raw_type":"text"},{"id":"pmh:oai:infoscience.epfl.ch:97036","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/97036","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:97036","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/97036","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W158833317","https://openalex.org/W1526252644","https://openalex.org/W2032094184","https://openalex.org/W2033045135","https://openalex.org/W2102727118","https://openalex.org/W2108730429","https://openalex.org/W2117602593","https://openalex.org/W2129763083","https://openalex.org/W2131239505","https://openalex.org/W2131308327","https://openalex.org/W2132700530","https://openalex.org/W2133393645","https://openalex.org/W2138351227","https://openalex.org/W2140137324","https://openalex.org/W2141112086","https://openalex.org/W2141242940","https://openalex.org/W2141718959","https://openalex.org/W2156979478","https://openalex.org/W2159617380","https://openalex.org/W2167857132","https://openalex.org/W3140903683","https://openalex.org/W4241323966","https://openalex.org/W4245298162","https://openalex.org/W4246334093","https://openalex.org/W4254014143","https://openalex.org/W4254415000","https://openalex.org/W6631475084","https://openalex.org/W6680948651","https://openalex.org/W6683257008","https://openalex.org/W6792941224"],"related_works":["https://openalex.org/W1916582918","https://openalex.org/W1905744402","https://openalex.org/W4250432526","https://openalex.org/W2101536355","https://openalex.org/W1595275176","https://openalex.org/W1934130410","https://openalex.org/W2562747857","https://openalex.org/W2112915496","https://openalex.org/W4243970730","https://openalex.org/W2150776253"],"abstract_inverted_index":{"We":[0,31],"analyze":[1],"an":[2,66,110],"Alpha":[3,74],"21264-like":[4,75],"globally-asynchronous,":[5],"locally-synchronous":[6],"(GALS)":[7],"processor":[8,23],"organized":[9],"as":[10,109,114,116],"multiple":[11],"clock":[12],"domain":[13],"(MCD)":[14],"microarchitecture":[15],"and":[16,87],"identify":[17],"the":[18,22,26,34,52,57,62,70,81,119],"architectural":[19],"features":[20,38,54],"of":[21,39,61,65,72,80,118],"that":[24,33,55,97],"influence":[25],"limited":[27],"performance":[28,58,120],"degradation":[29,59,121],"measured.":[30],"show":[32,96],"out-of-order":[35,100],"superscalar":[36,101],"execution":[37,46,102],"a":[40,105],"processor,":[41,76,113],"which":[42],"allow":[43],"traditional":[44],"instruction":[45],"latency":[47],"to":[48,78,104],"be":[49,127],"hidden,":[50],"are":[51,85],"same":[53],"reduce":[56],"impact":[60,90],"synchronization":[63,83,124],"costs":[64],"MCD":[67,82],"processor.":[68],"In":[69,93],"case":[71],"our":[73],"up":[77],"94%":[79],"delays":[84,125],"hidden":[86],"do":[88],"not":[89],"overall":[91],"performance.":[92],"addition,":[94],"we":[95],"by":[98,123],"adding":[99],"capabilities":[103],"simpler":[106],"microarchitecture,":[107],"such":[108],"Intel":[111],"StrongARM-like":[112],"much":[115],"62%":[117],"caused":[122],"can":[126],"eliminated.":[128]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}