{"id":"https://openalex.org/W1839397954","doi":"https://doi.org/10.1109/async.2004.1299294","title":"A general purpose behavioural asynchronous synthesis system","display_name":"A general purpose behavioural asynchronous synthesis system","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W1839397954","doi":"https://doi.org/10.1109/async.2004.1299294","mag":"1839397954"},"language":"en","primary_location":{"id":"doi:10.1109/async.2004.1299294","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2004.1299294","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075985354","display_name":"M. Sacker","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Sacker","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060418055","display_name":"A.D. Brown","orcid":"https://orcid.org/0000-0002-0700-9433"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A.D. Brown","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034122422","display_name":"Peter Wilson","orcid":"https://orcid.org/0000-0002-3611-0602"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P.R. Wilson","raw_affiliation_strings":["Department of Electronic & Electrical Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic & Electrical Engineering","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049623767","display_name":"Andrew Rushton","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A.J. Rushton","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"18","issue":null,"first_page":"125","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8687591552734375},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7933863401412964},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.7171244621276855},{"id":"https://openalex.org/keywords/synchronizing","display_name":"Synchronizing","score":0.6799483299255371},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.5731901526451111},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5569244027137756},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5239179730415344},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.505969226360321},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.505158007144928},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.48209813237190247},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.43715110421180725},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.4152262508869171},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.38354164361953735},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3653239905834198},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34188222885131836},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3015795648097992},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.29035088419914246},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.18931257724761963},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1769789457321167}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8687591552734375},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7933863401412964},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.7171244621276855},{"id":"https://openalex.org/C162932704","wikidata":"https://www.wikidata.org/wiki/Q1058791","display_name":"Synchronizing","level":3,"score":0.6799483299255371},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.5731901526451111},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5569244027137756},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5239179730415344},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.505969226360321},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.505158007144928},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.48209813237190247},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.43715110421180725},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.4152262508869171},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.38354164361953735},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3653239905834198},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34188222885131836},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3015795648097992},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.29035088419914246},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.18931257724761963},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1769789457321167},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/async.2004.1299294","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2004.1299294","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:eprints.soton.ac.uk:259371","is_oa":false,"landing_page_url":"https://eprints.soton.ac.uk/259371/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401020","display_name":"ePrints Soton (University of Southampton)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I43439940","host_organization_name":"University of Southampton","host_organization_lineage":["https://openalex.org/I43439940"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference or Workshop Item"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320006","display_name":"Royal Society","ror":"https://ror.org/03wnrjx87"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":49,"referenced_works":["https://openalex.org/W34100927","https://openalex.org/W122486620","https://openalex.org/W195428463","https://openalex.org/W1557441784","https://openalex.org/W1577323490","https://openalex.org/W1582258944","https://openalex.org/W1665361481","https://openalex.org/W1987980734","https://openalex.org/W1996109622","https://openalex.org/W2033422633","https://openalex.org/W2058948603","https://openalex.org/W2077649658","https://openalex.org/W2087765167","https://openalex.org/W2093032919","https://openalex.org/W2093842169","https://openalex.org/W2102612783","https://openalex.org/W2103499632","https://openalex.org/W2106923719","https://openalex.org/W2111388981","https://openalex.org/W2117602593","https://openalex.org/W2121914493","https://openalex.org/W2122623069","https://openalex.org/W2129183345","https://openalex.org/W2136757500","https://openalex.org/W2137978379","https://openalex.org/W2148539393","https://openalex.org/W2157753982","https://openalex.org/W2160160584","https://openalex.org/W2160823654","https://openalex.org/W2161247343","https://openalex.org/W2161884300","https://openalex.org/W2167577695","https://openalex.org/W2168226272","https://openalex.org/W2358486300","https://openalex.org/W2537389385","https://openalex.org/W2914903263","https://openalex.org/W4231905827","https://openalex.org/W4246266948","https://openalex.org/W4254415000","https://openalex.org/W4255981596","https://openalex.org/W4285719527","https://openalex.org/W4298011152","https://openalex.org/W6601411732","https://openalex.org/W6604992771","https://openalex.org/W6607902877","https://openalex.org/W6637168539","https://openalex.org/W6673841727","https://openalex.org/W6683394555","https://openalex.org/W6683425169"],"related_works":["https://openalex.org/W364924225","https://openalex.org/W60393894","https://openalex.org/W2095703739","https://openalex.org/W1993985975","https://openalex.org/W2093992207","https://openalex.org/W2325117947","https://openalex.org/W628161287","https://openalex.org/W158833317","https://openalex.org/W794031490","https://openalex.org/W2349909378"],"abstract_inverted_index":{"This":[0,228],"paper":[1,229],"describes":[2],"a":[3,16,82,94,177],"behavioural":[4],"asynchronous":[5,21,48,61],"synthesis":[6,215,234],"system":[7,84,105,210],"that":[8,47,191],"takes":[9],"as":[10,158,160,243,245],"input":[11],"an":[12,20],"algorithmic":[13],"description":[14],"of":[15,81,101,133,169,180,206,222,226,235,252],"design":[17,221],"and":[18,31,171,238],"produces":[19],"structural":[22],"implementation.":[23],"Several":[24],"example":[25],"systems":[26,49],"are":[27,75,149],"synthesized":[28],"both":[29],"synchronously":[30],"asynchronously":[32],"(with":[33],"no":[34],"modification":[35],"to":[36,78,108,156,204,219,255],"the":[37,44,60,79,86,99,104,119,131,134,138,144,147,154,161,167,173,189,192,199,202,209,220,233,246],"high":[38],"level":[39],"description).":[40],"In":[41],"keeping":[42],"with":[43,188],"well-established":[45],"observation":[46],"operate":[50,64],"at":[51],"average":[52],"case":[53],"time":[54,107,121],"complexity":[55],"rather":[56],"than":[57,68],"worse":[58],"case,":[59],"structures":[62],"usually":[63],"some":[65,109],"30%":[66],"faster":[67],"their":[69],"synchronous":[70,83],"counterparts,":[71],"although":[72],"interesting":[73],"counterexamples":[74],"observed.":[76],"Key":[77],"operation":[80],"is":[85,92,116,163,251],"(automatically":[87],"generated)":[88],"control":[89,174,237],"graph,":[90],"which":[91,250],"effectively":[93,128,186],"complex":[95],"sequence":[96],"generator":[97],"controlling":[98],"passage":[100],"data":[102,148,162,239],"through":[103],"in":[106,137],"synchronizing":[110],"clock.":[111],"The":[112],"maximum":[113],"clock":[114],"speed":[115],"dictated":[117],"by":[118,165],"slowest":[120],"slot.":[122],"Timeslots":[123],"containing":[124],"quicker":[125],"(less)":[126],"logic":[127,136],"waste":[129],"time:":[130],"output":[132],"combinational":[135],"state":[139,155,182],"have":[140],"settled":[141],"long":[142],"before":[143],"registers":[145],"reading":[146],"enabled.":[150],"If":[151],"we":[152],"allow":[153],"change":[157],"soon":[159],"ready,":[164],"introducing":[166],"concepts":[168],"'ready'":[170],"'acknowledge',":[172],"graph":[175],"becomes":[176,211],"disjoint":[178],"set":[179],"single":[181],"machines":[183],"-":[184],"it":[185],"disappears,":[187],"consequence":[190],"timeslot-timeslot":[193],"transitions":[194],"become":[195],"self-controlling.":[196],"Having":[197],"removed":[198],"necessity":[200],"for":[201,232],"timeslots":[203],"be":[205,217],"equal":[207],"duration":[208],"self-timing:":[212],"asynchronous.":[213],"Behavioural":[214],"can":[216],"applied":[218],"many":[223],"different":[224],"types":[225],"circuits.":[227],"includes":[230],"results":[231],"general":[236],"path":[240],"intensive":[241],"circuits":[242],"well":[244],"DES":[247],"cryptography":[248],"block,":[249],"particular":[253],"interest":[254],"those":[256],"designing":[257],"secure":[258],"embedded":[259],"products.":[260]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}