{"id":"https://openalex.org/W2130494408","doi":"https://doi.org/10.1109/async.2003.1199170","title":"Monotonic circuits with complete acknowledgement","display_name":"Monotonic circuits with complete acknowledgement","publication_year":2003,"publication_date":"2003-10-08","ids":{"openalex":"https://openalex.org/W2130494408","doi":"https://doi.org/10.1109/async.2003.1199170","mag":"2130494408"},"language":"en","primary_location":{"id":"doi:10.1109/async.2003.1199170","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2003.1199170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010552460","display_name":"N. Starodoubtsev","orcid":null},"institutions":[{"id":"https://openalex.org/I107165708","display_name":"Tokyo University of Social Welfare","ror":"https://ror.org/049fvjs25","country_code":"JP","type":"education","lineage":["https://openalex.org/I107165708"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"N. Starodoubtsev","raw_affiliation_strings":["Tokyo University of Social Welfare, Isesaki, Gunma, Japan","Tokyo Univ. of Social Welfare, Gunma, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo University of Social Welfare, Isesaki, Gunma, Japan","institution_ids":["https://openalex.org/I107165708"]},{"raw_affiliation_string":"Tokyo Univ. of Social Welfare, Gunma, Japan","institution_ids":["https://openalex.org/I107165708"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005799992","display_name":"Sergey Bystrov","orcid":"https://orcid.org/0009-0008-6525-0517"},"institutions":[{"id":"https://openalex.org/I4210120031","display_name":"Institute for Analytical Instrumentation","ror":"https://ror.org/02h6vef88","country_code":"RU","type":"facility","lineage":["https://openalex.org/I1313323035","https://openalex.org/I4210097085","https://openalex.org/I4210120031"]},{"id":"https://openalex.org/I1313323035","display_name":"Russian Academy of Sciences","ror":"https://ror.org/05qrfxd25","country_code":"RU","type":"funder","lineage":["https://openalex.org/I1313323035"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"S. Bystrov","raw_affiliation_strings":["Institute for Analytical Instrumentation of Russian, Russian Academy of Science, Saint Petersburg, Russia","Russian Academy of Science#TAB#"],"affiliations":[{"raw_affiliation_string":"Institute for Analytical Instrumentation of Russian, Russian Academy of Science, Saint Petersburg, Russia","institution_ids":["https://openalex.org/I4210120031"]},{"raw_affiliation_string":"Russian Academy of Science#TAB#","institution_ids":["https://openalex.org/I1313323035"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029446985","display_name":"Alex Yakovlev","orcid":"https://orcid.org/0000-0003-0826-9330"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A. Yakovlev","raw_affiliation_strings":["School of Electrical, Electronic and Computer Engineering, University of Newcastle, Newcastle-upon-Tyne, UK","University of Newcastle upon Tyne\u2020"],"affiliations":[{"raw_affiliation_string":"School of Electrical, Electronic and Computer Engineering, University of Newcastle, Newcastle-upon-Tyne, UK","institution_ids":["https://openalex.org/I84884186"]},{"raw_affiliation_string":"University of Newcastle upon Tyne\u2020","institution_ids":["https://openalex.org/I84884186"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5010552460"],"corresponding_institution_ids":["https://openalex.org/I107165708"],"apc_list":null,"apc_paid":null,"fwci":1.3909,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.8251104,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"23","issue":null,"first_page":"98","last_page":"108"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.7027392387390137},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5683743953704834},{"id":"https://openalex.org/keywords/monotonic-function","display_name":"Monotonic function","score":0.5638102293014526},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5211160778999329},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5126456618309021},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.4642043709754944},{"id":"https://openalex.org/keywords/acknowledgement","display_name":"Acknowledgement","score":0.462171733379364},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45490771532058716},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.4115745723247528},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3053484559059143},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2954355478286743},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1957000195980072},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1667424440383911},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0902300477027893}],"concepts":[{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.7027392387390137},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5683743953704834},{"id":"https://openalex.org/C72169020","wikidata":"https://www.wikidata.org/wiki/Q194404","display_name":"Monotonic function","level":2,"score":0.5638102293014526},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5211160778999329},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5126456618309021},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.4642043709754944},{"id":"https://openalex.org/C2777880217","wikidata":"https://www.wikidata.org/wiki/Q4674282","display_name":"Acknowledgement","level":2,"score":0.462171733379364},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45490771532058716},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.4115745723247528},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3053484559059143},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2954355478286743},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1957000195980072},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1667424440383911},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0902300477027893},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.2003.1199170","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2003.1199170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1491226430","https://openalex.org/W1568028524","https://openalex.org/W1634760171","https://openalex.org/W1981519869","https://openalex.org/W2047298212","https://openalex.org/W2073076521","https://openalex.org/W2130434989","https://openalex.org/W2134829921","https://openalex.org/W2147953779","https://openalex.org/W6629326351","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W1504381137","https://openalex.org/W4283656061","https://openalex.org/W2620413320","https://openalex.org/W3102611879","https://openalex.org/W4385757279","https://openalex.org/W2067129656","https://openalex.org/W3144289157","https://openalex.org/W3010731809","https://openalex.org/W2046896068","https://openalex.org/W1962044841"],"abstract_inverted_index":{"The":[0,72,97],"paper":[1,73],"studies":[2],"a":[3,87,94,102],"class":[4],"of":[5,16,41,59,78,86,99,101,104,121,137],"asynchronous":[6],"circuits":[7,38,54,82,143],"in":[8,129],"which":[9],"every":[10,17],"signal":[11],"transition":[12],"on":[13],"the":[14,22,55,75,84,119,133],"inputs":[15],"gate":[18,114],"is":[19,27,34],"acknowledged":[20],"during":[21],"circuit":[23],"operation.":[24],"This":[25],"property":[26],"called":[28],"complete":[29],"acknowledgement":[30],"(CA)":[31],"and":[32,83,135,139],"it":[33],"considered":[35],"here":[36],"for":[37,70,147],"that":[39],"consist":[40],"gates":[42,62],"described":[43],"by":[44,65,112],"monotonic":[45,79],"Boolean":[46],"functions":[47],"only.":[48],"In":[49],"order":[50],"to":[51,90,93,127],"implement":[52],"such":[53,142],"standard":[56],"CMOS":[57,149],"designs":[58],"2-input":[60],"logic":[61],"are":[63],"modified":[64],"using":[66],"an":[67],"additional":[68],"output":[69],"CA.":[71],"investigates":[74],"behavioral":[76,88],"properties":[77],"CA":[80,105,122],"(MCA)":[81],"feasibility":[85],"specification":[89],"be":[91],"refined":[92],"CA-implementable":[95],"form.":[96],"result":[98],"comparison":[100],"number":[103],"realizations":[106],"with":[107],"their":[108],"speed-independent":[109],"counterparts":[110],"produced":[111],"negative":[113],"synthesis":[115],"inspires":[116],"optimism":[117],"about":[118],"practicality":[120],"circuits.":[123],"Being":[124],"particularly":[125],"robust":[126],"variations":[128],"technological":[130],"parameters,":[131],"e.g.":[132],"value":[134],"type":[136],"delay":[138],"switching":[140],"thresholds,":[141],"offer":[144],"potential":[145],"advantages":[146],"future":[148],"designs.":[150]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}