{"id":"https://openalex.org/W2131249667","doi":"https://doi.org/10.1109/async.2002.1000305","title":"Checking delay-insensitivity: 10/sup 4/ gates and beyond","display_name":"Checking delay-insensitivity: 10/sup 4/ gates and beyond","publication_year":2004,"publication_date":"2004-04-23","ids":{"openalex":"https://openalex.org/W2131249667","doi":"https://doi.org/10.1109/async.2002.1000305","mag":"2131249667"},"language":"en","primary_location":{"id":"doi:10.1109/async.2002.1000305","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2002.1000305","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Eighth International Symposium on Asynchronous Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069752974","display_name":"A. Kondratyev","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Kondratyev","raw_affiliation_strings":["Cadence Berkeley Laboratories, USA","Cadence Berkeley Lab., USA"],"affiliations":[{"raw_affiliation_string":"Cadence Berkeley Laboratories, USA","institution_ids":["https://openalex.org/I66217453","https://openalex.org/I148283060"]},{"raw_affiliation_string":"Cadence Berkeley Lab., USA","institution_ids":["https://openalex.org/I66217453","https://openalex.org/I148283060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058139808","display_name":"Lawrence Neukom","orcid":null},"institutions":[{"id":"https://openalex.org/I4210161168","display_name":"Runtime Verification (United States)","ror":"https://ror.org/04gmecg65","country_code":"US","type":"company","lineage":["https://openalex.org/I4210161168"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. Neukom","raw_affiliation_strings":["Verific Design Automation, USA","[Verific Design Automation, USA]"],"affiliations":[{"raw_affiliation_string":"Verific Design Automation, USA","institution_ids":["https://openalex.org/I4210161168"]},{"raw_affiliation_string":"[Verific Design Automation, USA]","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011169484","display_name":"O. Roig","orcid":"https://orcid.org/0000-0001-8402-4760"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I4210108428","display_name":"Cadence Biomedical (United States)","ror":"https://ror.org/01vj62p39","country_code":"US","type":"company","lineage":["https://openalex.org/I4210108428"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"O. Roig","raw_affiliation_strings":["Cadence Technology, USA","[Cadence Technology, USA]"],"affiliations":[{"raw_affiliation_string":"Cadence Technology, USA","institution_ids":["https://openalex.org/I66217453","https://openalex.org/I4210108428"]},{"raw_affiliation_string":"[Cadence Technology, USA]","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040984542","display_name":"Alexander Taubin","orcid":null},"institutions":[{"id":"https://openalex.org/I111088046","display_name":"Boston University","ror":"https://ror.org/05qwgg493","country_code":"US","type":"education","lineage":["https://openalex.org/I111088046"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Taubin","raw_affiliation_strings":["Boston University, USA","[Boston University, USA]"],"affiliations":[{"raw_affiliation_string":"Boston University, USA","institution_ids":["https://openalex.org/I111088046"]},{"raw_affiliation_string":"[Boston University, USA]","institution_ids":["https://openalex.org/I111088046"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057674619","display_name":"Karl M. Fant","orcid":"https://orcid.org/0000-0003-0951-2136"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K. Fant","raw_affiliation_strings":["Theseus Research","[Theseus Research]"],"affiliations":[{"raw_affiliation_string":"Theseus Research","institution_ids":[]},{"raw_affiliation_string":"[Theseus Research]","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5069752974"],"corresponding_institution_ids":["https://openalex.org/I148283060","https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":4.0457,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.94044848,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"149","last_page":"157"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6738266944885254},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6602100133895874},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5636448860168457},{"id":"https://openalex.org/keywords/satisfiability","display_name":"Satisfiability","score":0.49425506591796875},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.48491841554641724},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47888749837875366},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4254017174243927},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.42223986983299255},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3747614622116089},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3727263808250427},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3433365821838379},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.31995829939842224},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31433969736099243},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.2678769826889038},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21248504519462585},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15460455417633057},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14210256934165955}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6738266944885254},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6602100133895874},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5636448860168457},{"id":"https://openalex.org/C168773769","wikidata":"https://www.wikidata.org/wiki/Q1350299","display_name":"Satisfiability","level":2,"score":0.49425506591796875},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.48491841554641724},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47888749837875366},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4254017174243927},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.42223986983299255},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3747614622116089},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3727263808250427},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3433365821838379},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.31995829939842224},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31433969736099243},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.2678769826889038},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21248504519462585},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15460455417633057},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14210256934165955},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.2002.1000305","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2002.1000305","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Eighth International Symposium on Asynchronous Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1483902580","https://openalex.org/W1491037212","https://openalex.org/W1503170978","https://openalex.org/W1513324186","https://openalex.org/W1568729458","https://openalex.org/W1585465727","https://openalex.org/W1665361481","https://openalex.org/W1765538419","https://openalex.org/W1999082644","https://openalex.org/W2016300863","https://openalex.org/W2033724727","https://openalex.org/W2048051309","https://openalex.org/W2093709900","https://openalex.org/W2098326421","https://openalex.org/W2106950603","https://openalex.org/W2108432348","https://openalex.org/W2111125619","https://openalex.org/W2114092850","https://openalex.org/W2115264823","https://openalex.org/W2117299791","https://openalex.org/W2132472209","https://openalex.org/W2137035823","https://openalex.org/W2137978379","https://openalex.org/W2142785340","https://openalex.org/W2160444875","https://openalex.org/W2160823654","https://openalex.org/W2169131413","https://openalex.org/W2344671925","https://openalex.org/W4229840182","https://openalex.org/W4243399171","https://openalex.org/W6637168539","https://openalex.org/W6637799165","https://openalex.org/W6658919716","https://openalex.org/W6683394555","https://openalex.org/W6704706996","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W3176904788","https://openalex.org/W21597398","https://openalex.org/W4298153058","https://openalex.org/W2408080066","https://openalex.org/W2268872489","https://openalex.org/W1913543287","https://openalex.org/W2014111643","https://openalex.org/W2963044240","https://openalex.org/W2076399409","https://openalex.org/W2102364390"],"abstract_inverted_index":{"Wire":[0],"and":[1,73],"gate":[2],"delays":[3,35],"are":[4],"accounted":[5],"to":[6,26],"have":[7],"equal,":[8,11],"or":[9],"nearly":[10],"effect":[12],"on":[13,77],"circuit":[14],"behavior":[15,30],"in":[16],"modern":[17],"design":[18,79],"techniques.":[19],"This":[20,65],"paper":[21],"introduces":[22],"a":[23,41,46,50],"new":[24],"approach":[25],"verifying":[27],"circuits":[28],"whose":[29],"is":[31,67,74],"independent":[32],"of":[33,44,57,83,85],"component":[34],"(delay-insensitive).":[36],"It":[37],"shows":[38],"that":[39],"for":[40],"particular":[42],"way":[43],"implementing":[45],"delay-insensitive":[47],"circuit,":[48],"through":[49],"Null":[51],"Convention":[52],"Logic":[53],"methodology,":[54],"the":[55,58],"complexity":[56],"verification":[59],"task":[60],"might":[61],"be":[62],"significantly":[63],"reduced.":[64],"method":[66],"implemented":[68],"using":[69],"Satisfiability":[70],"(SAT)":[71],"solvers":[72],"successfully":[75],"tested":[76],"realistic":[78],"examples":[80],"having":[81],"tens":[82],"thousands":[84],"gates.":[86]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}