{"id":"https://openalex.org/W2118051980","doi":"https://doi.org/10.1109/async.2002.1000304","title":"Design and performance analysis of buffers: a constructive approach","display_name":"Design and performance analysis of buffers: a constructive approach","publication_year":2004,"publication_date":"2004-04-23","ids":{"openalex":"https://openalex.org/W2118051980","doi":"https://doi.org/10.1109/async.2002.1000304","mag":"2118051980"},"language":"en","primary_location":{"id":"doi:10.1109/async.2002.1000304","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2002.1000304","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Eighth International Symposium on Asynchronous Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002414836","display_name":"Rudolf H. Mak","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"R.H. Mak","raw_affiliation_strings":["Department of Mathematics and Computing Science, Technische Universiteit Eindhoven, Eindhoven, Netherlands","Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Mathematics and Computing Science, Technische Universiteit Eindhoven, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands","institution_ids":["https://openalex.org/I83019370"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5002414836"],"corresponding_institution_ids":["https://openalex.org/I83019370"],"apc_list":null,"apc_paid":null,"fwci":0.5282,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.66723591,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5","issue":null,"first_page":"137","last_page":"148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.9179338216781616},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7199385166168213},{"id":"https://openalex.org/keywords/formalism","display_name":"Formalism (music)","score":0.6417052745819092},{"id":"https://openalex.org/keywords/constructive","display_name":"Constructive","score":0.5934905409812927},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.5894941091537476},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5755204558372498},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46553292870521545},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4631037414073944},{"id":"https://openalex.org/keywords/range","display_name":"Range (aeronautics)","score":0.4476607143878937},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.42243343591690063},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42193999886512756},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3943209946155548},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.256813645362854},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15798816084861755},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13141652941703796},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08690351247787476}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.9179338216781616},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7199385166168213},{"id":"https://openalex.org/C73301696","wikidata":"https://www.wikidata.org/wiki/Q5469984","display_name":"Formalism (music)","level":3,"score":0.6417052745819092},{"id":"https://openalex.org/C2778701210","wikidata":"https://www.wikidata.org/wiki/Q28130034","display_name":"Constructive","level":3,"score":0.5934905409812927},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.5894941091537476},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5755204558372498},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46553292870521545},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4631037414073944},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.4476607143878937},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.42243343591690063},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42193999886512756},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3943209946155548},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.256813645362854},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15798816084861755},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13141652941703796},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08690351247787476},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.0},{"id":"https://openalex.org/C558565934","wikidata":"https://www.wikidata.org/wiki/Q2743","display_name":"Musical","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/async.2002.1000304","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2002.1000304","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Eighth International Symposium on Asynchronous Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/849a5f9c-ded8-49a2-80d1-ea915661b474","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/849a5f9c-ded8-49a2-80d1-ea915661b474","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Mak, R H 2002, Design and performance analysis of buffers: a constructive approach. in Proceedings 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002, Manchester, UK, April 9-11, 2002). IEEE Computer Society, Los Alamitos CA, pp. 137-148. https://doi.org/10.1109/ASYNC.2002.1000304","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:library.tue.nl:660619","is_oa":false,"landing_page_url":"http://repository.tue.nl/660619","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""},{"id":"pmh:tue:oai:pure.tue.nl:publications/849a5f9c-ded8-49a2-80d1-ea915661b474","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/849a5f9c-ded8-49a2-80d1-ea915661b474","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002, Manchester, UK, April 9-11, 2002), 137 - 148","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1723577572","https://openalex.org/W1914036602","https://openalex.org/W1998667371","https://openalex.org/W2101606227","https://openalex.org/W2109341366","https://openalex.org/W2149872541","https://openalex.org/W2160104413","https://openalex.org/W2164116916","https://openalex.org/W2171911180","https://openalex.org/W2295534994","https://openalex.org/W2392726451","https://openalex.org/W2589217375","https://openalex.org/W6679167927","https://openalex.org/W6685608348"],"related_works":["https://openalex.org/W3008339103","https://openalex.org/W2404647514","https://openalex.org/W1667647204","https://openalex.org/W4247536566","https://openalex.org/W3119814709","https://openalex.org/W2018477250","https://openalex.org/W1508895727","https://openalex.org/W4241418540","https://openalex.org/W2725786787","https://openalex.org/W4283160672"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,53,62,92],"theoretical":[4],"framework":[5],"to":[6,16,37,55],"analyse":[7],"the":[8,18,21,39,71,79,85,105,109,112],"correctness":[9,41],"of":[10,20,29,42,58,73,84,95,111,114],"VLSI":[11],"programs":[12],"for":[13,64],"buffers":[14],"and":[15,60,88],"compare":[17],"performance":[19,65],"corresponding":[22],"circuits.":[23],"A":[24],"very":[25],"simple":[26],"calculus":[27],"consisting":[28],"only":[30],"two":[31],"operators":[32],"is":[33,68,76],"presented":[34,50],"that":[35,70,81,116],"suffices":[36],"establish":[38],"functional":[40],"complicated":[43],"buffer":[44,83],"designs.":[45],"Furthermore,":[46],"sequence":[47],"functions":[48],"are":[49],"both":[51],"as":[52,61],"formalism":[54],"show":[56],"absence":[57],"deadlock":[59],"vehicle":[63],"analysis.":[66],"It":[67],"shown":[69],"class":[72],"square":[74],"FIFOs":[75],"optimal":[77],"in":[78],"sense":[80],"no":[82],"same":[86],"capacity":[87],"I/O-distance":[89],"can":[90],"accommodate":[91],"larger":[93],"range":[94,113],"occupancies,":[96],"when":[97],"run":[98],"at":[99],"its":[100],"minimum":[101],"cycle":[102],"time.":[103],"Moreover,":[104],"theory":[106],"accurately":[107],"predicts":[108],"size":[110],"occupancies":[115],"has":[117],"been":[118],"found":[119],"experimentally.":[120]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
