{"id":"https://openalex.org/W2120750303","doi":"https://doi.org/10.1109/async.2002.1000303","title":"Asynchronous circuit synthesis by direct mapping: interfacing to environment","display_name":"Asynchronous circuit synthesis by direct mapping: interfacing to environment","publication_year":2004,"publication_date":"2004-04-23","ids":{"openalex":"https://openalex.org/W2120750303","doi":"https://doi.org/10.1109/async.2002.1000303","mag":"2120750303"},"language":"en","primary_location":{"id":"doi:10.1109/async.2002.1000303","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2002.1000303","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Eighth International Symposium on Asynchronous Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043467352","display_name":"A. Bystrov","orcid":"https://orcid.org/0000-0001-9338-2535"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"A. Bystrov","raw_affiliation_strings":["University of Newcastle, UK","[Newcastle upon Tyne University, UK]"],"affiliations":[{"raw_affiliation_string":"University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]},{"raw_affiliation_string":"[Newcastle upon Tyne University, UK]","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029446985","display_name":"Alex Yakovlev","orcid":"https://orcid.org/0000-0003-0826-9330"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A. Yakovlev","raw_affiliation_strings":["University of Newcastle, UK","[Newcastle upon Tyne University, UK]"],"affiliations":[{"raw_affiliation_string":"University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]},{"raw_affiliation_string":"[Newcastle upon Tyne University, UK]","institution_ids":["https://openalex.org/I84884186"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5043467352"],"corresponding_institution_ids":["https://openalex.org/I84884186"],"apc_list":null,"apc_paid":null,"fwci":5.0571,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.95708203,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"127","last_page":"136"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.7625478506088257},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7497178316116333},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7180975079536438},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6922217607498169},{"id":"https://openalex.org/keywords/petri-net","display_name":"Petri net","score":0.556017279624939},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5132608413696289},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5122081637382507},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5072009563446045},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.46630704402923584},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.4429929852485657},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33320438861846924},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2771131098270416},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.266202837228775},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.21227926015853882},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.15109774470329285},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.10043209791183472},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.09356200695037842}],"concepts":[{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.7625478506088257},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7497178316116333},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7180975079536438},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6922217607498169},{"id":"https://openalex.org/C38677869","wikidata":"https://www.wikidata.org/wiki/Q724168","display_name":"Petri net","level":2,"score":0.556017279624939},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5132608413696289},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5122081637382507},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5072009563446045},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.46630704402923584},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.4429929852485657},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33320438861846924},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2771131098270416},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.266202837228775},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.21227926015853882},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.15109774470329285},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.10043209791183472},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.09356200695037842},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.2002.1000303","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2002.1000303","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Eighth International Symposium on Asynchronous Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W77906453","https://openalex.org/W258022877","https://openalex.org/W1491226430","https://openalex.org/W1498870363","https://openalex.org/W1502716092","https://openalex.org/W1503973138","https://openalex.org/W1558392573","https://openalex.org/W1563467089","https://openalex.org/W1570043190","https://openalex.org/W1585465727","https://openalex.org/W1665361481","https://openalex.org/W2014984434","https://openalex.org/W2033724727","https://openalex.org/W2044146671","https://openalex.org/W2089904802","https://openalex.org/W2106929737","https://openalex.org/W2160823654","https://openalex.org/W2161331676","https://openalex.org/W2169318778","https://openalex.org/W2296054660","https://openalex.org/W2914903263","https://openalex.org/W3142103469","https://openalex.org/W3177082579","https://openalex.org/W6603190525","https://openalex.org/W6629326351","https://openalex.org/W6629985922","https://openalex.org/W6630104300","https://openalex.org/W6633972513","https://openalex.org/W6658919716","https://openalex.org/W6672993756","https://openalex.org/W6683394555","https://openalex.org/W6697480532","https://openalex.org/W6884906308","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W1525970584","https://openalex.org/W1984298705","https://openalex.org/W2165341302","https://openalex.org/W4247130854","https://openalex.org/W2364544765","https://openalex.org/W4212803501","https://openalex.org/W4313128371","https://openalex.org/W2127795343","https://openalex.org/W1482079447","https://openalex.org/W2140883893"],"abstract_inverted_index":{"Direct":[0],"mapping":[1,18,47],"helps":[2],"avoid":[3],"algorithmic":[4],"complexity":[5],"which":[6],"is":[7,64,139],"inherent":[8],"in":[9,30,111,135],"logic":[10,34,134,147],"synthesis":[11,148],"methods.":[12],"However,":[13],"existing":[14],"techniques":[15],"for":[16,49,166],"direct":[17,46],"of":[19,97,105,114,132],"Petri":[20],"net":[21],"specifications":[22],"to":[23,33,39,71,86,90,120,146],"asynchronous":[24],"control":[25,113],"circuit":[26,123],"do":[27],"not":[28],"deliver":[29],"performance":[31],"due":[32],"overhead":[35],"and":[36,60,78,108,154,168],"inefficient":[37],"interface":[38,84],"the":[40,72,103,106,112,115,122,136],"environment.":[41],"The":[42,81,93,130,144,157],"paper":[43],"presents":[44],"a":[45],"method":[48,160],"Signal":[50],"Transition":[51],"Graphs":[52],"(STGs)":[53],"targetted":[54],"at":[55],"lower":[56,151],"latency":[57,153],"between":[58],"input":[59,109],"output":[61,76,116,152,169],"events.":[62],"It":[63],"based":[65],"on":[66],"two":[67,142],"behaviour-preserving":[68],"transformations":[69],"applied":[70],"initial":[73],"STG":[74],"model:":[75],"exposition":[77],"environment":[79],"tracking.":[80],"former":[82],"allows":[83,161],"signals":[85,110,170],"be":[87],"generated":[88],"concurrently":[89],"internal":[91],"transitions.":[92],"latter":[94],"prevents":[95],"creation":[96],"coding":[98],"conflicts.":[99],"Subsequent":[100],"refinement":[101],"combines":[102],"use":[104],"tracking":[107,128,167],"flip-flops":[117],"so":[118],"as":[119],"optimise":[121],"size":[124],"by":[125],"removing":[126],"some":[127],"components.":[129],"depth":[131],"final":[133],"design":[137],"examples":[138],"one":[140],"or":[141],"gates.":[143],"comparison":[145],"methods":[149],"indicates":[150],"greater":[155],"size.":[156],"proposed":[158],"direct-mapping":[159],"using":[162],"fast":[163],"transistor-level":[164],"implementations":[165],"with":[171],"well-localised":[172],"relative":[173],"timing":[174],"constraints.":[175]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}