{"id":"https://openalex.org/W2103699587","doi":"https://doi.org/10.1109/async.2002.1000301","title":"Generation and verification of timing constraints for fine-grain pipelined asynchronous data-path circuits","display_name":"Generation and verification of timing constraints for fine-grain pipelined asynchronous data-path circuits","publication_year":2004,"publication_date":"2004-04-23","ids":{"openalex":"https://openalex.org/W2103699587","doi":"https://doi.org/10.1109/async.2002.1000301","mag":"2103699587"},"language":"en","primary_location":{"id":"doi:10.1109/async.2002.1000301","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2002.1000301","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Eighth International Symposium on Asynchronous Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029617836","display_name":"Metehan Ozcan","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Ozcan","raw_affiliation_strings":["Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","Research Center for Advanced Science and Technology University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Research Center for Advanced Science and Technology University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015068403","display_name":"Masayuki Imai","orcid":"https://orcid.org/0000-0002-1400-7794"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Imai","raw_affiliation_strings":["Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","Research Center for Advanced Science and Technology University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Research Center for Advanced Science and Technology University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073211567","display_name":"Takashi Nanya","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Nanya","raw_affiliation_strings":["Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","Research Center for Advanced Science and Technology University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Research Center for Advanced Science and Technology University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5029617836"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.6583,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72363649,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"109","last_page":"114"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8634172081947327},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8050611019134521},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6965845227241516},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.67735356092453},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6070370674133301},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5113901495933533},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4796231687068939},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3310794234275818},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32057511806488037},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.26526737213134766},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20754265785217285},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08260655403137207},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.079530268907547},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.07498279213905334}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8634172081947327},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8050611019134521},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6965845227241516},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.67735356092453},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6070370674133301},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5113901495933533},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4796231687068939},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3310794234275818},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32057511806488037},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.26526737213134766},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20754265785217285},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08260655403137207},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.079530268907547},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.07498279213905334},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.2002.1000301","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2002.1000301","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Eighth International Symposium on Asynchronous Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1546119310","https://openalex.org/W2104105510","https://openalex.org/W2121914493","https://openalex.org/W2135441328","https://openalex.org/W2141718959","https://openalex.org/W2911717499","https://openalex.org/W6678153968"],"related_works":["https://openalex.org/W1948903516","https://openalex.org/W1993985975","https://openalex.org/W2146990170","https://openalex.org/W2187164010","https://openalex.org/W4312516786","https://openalex.org/W2085028021","https://openalex.org/W2138474603","https://openalex.org/W3094139610","https://openalex.org/W937897205","https://openalex.org/W2362706271"],"abstract_inverted_index":{"Timing":[0],"analysis":[1,21],"is":[2],"a":[3,11,53],"method":[4],"for":[5,19,56],"verification":[6,60],"of":[7,61],"timing":[8,20],"constraints":[9,40,63],"in":[10,30,41,50],"digital":[12],"circuit.":[13],"Asynchronous":[14],"circuits":[15,47],"bring":[16],"new":[17],"concerns":[18],"with":[22,67],"their":[23],"local":[24],"completion":[25],"circuits,":[26],"which":[27],"generate":[28],"cycles":[29],"the":[31],"circuit":[32],"and":[33,52,59],"require":[34],"special":[35],"handling.":[36],"In":[37],"this":[38],"paper":[39],"fine":[42],"grain":[43],"pipelined":[44],"asynchronous":[45],"data-path":[46],"are":[48,64],"examined":[49],"detail":[51],"tool":[54],"environment":[55],"automatic":[57],"generation":[58],"these":[62],"presented":[65],"along":[66],"some":[68],"sample":[69],"layout":[70],"results.":[71]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
