{"id":"https://openalex.org/W2167775755","doi":"https://doi.org/10.1109/async.1999.761523","title":"RAPPID: an asynchronous instruction length decoder","display_name":"RAPPID: an asynchronous instruction length decoder","publication_year":2003,"publication_date":"2003-01-20","ids":{"openalex":"https://openalex.org/W2167775755","doi":"https://doi.org/10.1109/async.1999.761523","mag":"2167775755"},"language":"en","primary_location":{"id":"doi:10.1109/async.1999.761523","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.1999.761523","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000940067","display_name":"S. Rotem","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Rotem","raw_affiliation_strings":["Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113695022","display_name":"Kenneth S. Stevens","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Stevens","raw_affiliation_strings":["Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010407295","display_name":"Ran Ginosar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL","US"],"is_corresponding":false,"raw_author_name":"R. Ginosar","raw_affiliation_strings":["Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA","Technion, VLSI Systems Research Center, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Technion, VLSI Systems Research Center, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084205024","display_name":"Peter A. Beerel","orcid":"https://orcid.org/0000-0002-8283-0168"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Beerel","raw_affiliation_strings":["EE-Systems, University of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"EE-Systems, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111386695","display_name":"Chris J. Myers","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Myers","raw_affiliation_strings":["EE Department, University of Utah, Salt Lake, UT, USA"],"affiliations":[{"raw_affiliation_string":"EE Department, University of Utah, Salt Lake, UT, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003912143","display_name":"K.Y. Yun","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Yun","raw_affiliation_strings":["ECE Department, University of California, San Diego, CA, USA"],"affiliations":[{"raw_affiliation_string":"ECE Department, University of California, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000647499","display_name":"Rakefet Kol","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Kol","raw_affiliation_strings":["Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110263222","display_name":"C. Dike","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Dike","raw_affiliation_strings":["Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083773051","display_name":"Marly Roncken","orcid":"https://orcid.org/0000-0002-3703-3856"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Roncken","raw_affiliation_strings":["Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085672048","display_name":"B. Agapiev","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Agapiev","raw_affiliation_strings":["Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5000940067"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":7.9976,"has_fulltext":false,"cited_by_count":75,"citation_normalized_percentile":{"value":0.97924495,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"60","last_page":"70"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8065106868743896},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7966035604476929},{"id":"https://openalex.org/keywords/pentium","display_name":"Pentium","score":0.7840344905853271},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6044859886169434},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.5886173248291016},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5162677764892578},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47063112258911133},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4703519344329834},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45797204971313477},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4403395354747772},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4193084239959717},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4133360981941223},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35488906502723694},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.19587138295173645},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12874174118041992},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09562426805496216},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.06609058380126953}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8065106868743896},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7966035604476929},{"id":"https://openalex.org/C46268123","wikidata":"https://www.wikidata.org/wiki/Q214314","display_name":"Pentium","level":2,"score":0.7840344905853271},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6044859886169434},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5886173248291016},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5162677764892578},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47063112258911133},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4703519344329834},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45797204971313477},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4403395354747772},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4193084239959717},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4133360981941223},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35488906502723694},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.19587138295173645},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12874174118041992},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09562426805496216},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.06609058380126953},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.1999.761523","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.1999.761523","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W29127030","https://openalex.org/W1550487395","https://openalex.org/W1722620788","https://openalex.org/W1793691888","https://openalex.org/W2009210174","https://openalex.org/W2058948603","https://openalex.org/W2135367033","https://openalex.org/W2136310485","https://openalex.org/W2136757500","https://openalex.org/W2293601555","https://openalex.org/W2295079892"],"related_works":["https://openalex.org/W1597195064","https://openalex.org/W1545378222","https://openalex.org/W2915007006","https://openalex.org/W3164835776","https://openalex.org/W2230641373","https://openalex.org/W1560501822","https://openalex.org/W2129938370","https://openalex.org/W2039249740","https://openalex.org/W1980424176","https://openalex.org/W2038509808"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"an":[3,12,92],"investigation":[4],"of":[5,10,61],"potential":[6],"advantages":[7],"and":[8,33,52,76,85],"risks":[9,65],"applying":[11],"aggressive":[13],"asynchronous":[14],"design":[15,68],"methodology":[16],"to":[17],"Intel":[18],"Architecture.":[19],"RAPPID":[20,41,70],"(\"Revolving":[21],"Asynchronous":[22],"Pentium(R)":[23],"Processor":[24],"Instruction":[25],"Decoder\"),":[26],"a":[27,46],"prototype":[28],"IA32":[29],"instruction":[30],"length":[31],"decoding":[32],"steering":[34],"unit,":[35],"was":[36,43],"implemented":[37],"using":[38,66],"self-timed":[39],"techniques.":[40],"chip":[42],"fabricated":[44],"on":[45],"0.25":[47],"/spl":[48],"mu/":[49],"CMOS":[50],"process":[51],"tested":[53],"successfully.":[54],"Results":[55],"show":[56],"significant":[57],"advantages-in":[58],"particular,":[59],"performance":[60],"2.5-4.5":[62],"instructions/nS-with":[63],"manageable":[64],"this":[67],"technology.":[69],"achieves":[71],"three":[72],"times":[73],"the":[74,78,83,88],"throughput":[75],"half":[77,82],"latency,":[79],"dissipating":[80],"only":[81],"power":[84],"requiring":[86],"about":[87],"same":[89],"area":[90],"as":[91],"existing":[93],"400":[94],"MHz":[95],"clocked":[96],"circuit.":[97]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
