{"id":"https://openalex.org/W2907512792","doi":"https://doi.org/10.1109/asscc.2018.8579319","title":"Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F<sup>2</sup> and K-means Clustering for Power Reduction","display_name":"Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F<sup>2</sup> and K-means Clustering for Power Reduction","publication_year":2018,"publication_date":"2018-11-01","ids":{"openalex":"https://openalex.org/W2907512792","doi":"https://doi.org/10.1109/asscc.2018.8579319","mag":"2907512792"},"language":"en","primary_location":{"id":"doi:10.1109/asscc.2018.8579319","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asscc.2018.8579319","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085433686","display_name":"Keji Zhou","orcid":"https://orcid.org/0000-0002-3078-4542"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Keji Zhou","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034197769","display_name":"Xiaoyong Xue","orcid":"https://orcid.org/0000-0001-9001-4569"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyong Xue","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101691460","display_name":"Jianguo Yang","orcid":"https://orcid.org/0000-0001-9581-993X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianguo Yang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049920459","display_name":"Xiaoxin Xu","orcid":"https://orcid.org/0000-0002-0277-1314"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoxin Xu","raw_affiliation_strings":["Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111976023","display_name":"Hangbing Lv","orcid":"https://orcid.org/0000-0003-4727-9224"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hangbing Lv","raw_affiliation_strings":["Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100350102","display_name":"Mingyu Wang","orcid":"https://orcid.org/0000-0001-5722-9752"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mingyu Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041920474","display_name":"Mingre Jing","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mingre Jing","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100380194","display_name":"Wen-Jun Liu","orcid":"https://orcid.org/0000-0003-4217-8838"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wenjun Liu","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115590332","display_name":"Xiaoyang Zeng","orcid":"https://orcid.org/0000-0003-3986-137X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyang Zeng","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064704800","display_name":"Steve S. Chung","orcid":"https://orcid.org/0000-0002-1732-8518"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Steve S. Chung","raw_affiliation_strings":["National Chiao Tung University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100626667","display_name":"Jing Li","orcid":"https://orcid.org/0000-0001-5139-938X"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jing Li","raw_affiliation_strings":["University of Wisconsin, Madison, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100347765","display_name":"Ming Liu","orcid":"https://orcid.org/0000-0002-1114-1728"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ming Liu","raw_affiliation_strings":["Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I19820366"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"135","last_page":"138"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.7470613121986389},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.582709014415741},{"id":"https://openalex.org/keywords/content-addressable-memory","display_name":"Content-addressable memory","score":0.5583505034446716},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.541423499584198},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5402476787567139},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5180920958518982},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.49219265580177307},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.48343050479888916},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4654906988143921},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41279712319374084},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3665410280227661},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34093591570854187},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3065882921218872},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26491624116897583},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2159598469734192},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1479298174381256},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1441342532634735},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13541701436042786},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11310145258903503}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.7470613121986389},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.582709014415741},{"id":"https://openalex.org/C53442348","wikidata":"https://www.wikidata.org/wiki/Q745101","display_name":"Content-addressable memory","level":3,"score":0.5583505034446716},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.541423499584198},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5402476787567139},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5180920958518982},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.49219265580177307},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.48343050479888916},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4654906988143921},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41279712319374084},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3665410280227661},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34093591570854187},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3065882921218872},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26491624116897583},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2159598469734192},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1479298174381256},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1441342532634735},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13541701436042786},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11310145258903503},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asscc.2018.8579319","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asscc.2018.8579319","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8199999928474426,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1836287480","https://openalex.org/W1898756433","https://openalex.org/W1999458342","https://openalex.org/W2006232962","https://openalex.org/W2055411146","https://openalex.org/W2062143991","https://openalex.org/W2097203998","https://openalex.org/W2109041721","https://openalex.org/W2125693020","https://openalex.org/W2139118865","https://openalex.org/W2141298043","https://openalex.org/W2148256155","https://openalex.org/W2169801078","https://openalex.org/W2289106931","https://openalex.org/W2510418541","https://openalex.org/W6639975574","https://openalex.org/W6685169983"],"related_works":["https://openalex.org/W2145932742","https://openalex.org/W3005999147","https://openalex.org/W3176428941","https://openalex.org/W3089883684","https://openalex.org/W4232634182","https://openalex.org/W4301187613","https://openalex.org/W2923038022","https://openalex.org/W3008646524","https://openalex.org/W4385624997","https://openalex.org/W2593506445"],"abstract_inverted_index":{"A":[0],"28nm":[1],"16Kb":[2],"nonvolatile":[3],"ternary":[4],"content":[5],"addressable":[6],"memory":[7,15],"(nvTCAM)":[8],"test":[9],"chip":[10],"based":[11],"on":[12],"logic-compatible":[13],"resistive":[14],"(ReRAM)":[16],"is":[17,58],"demonstrated":[18],"with":[19,107],"high":[20],"density":[21,100],"and":[22,82,101],"low":[23],"power":[24,92],"for":[25,51,68,91,113],"packet":[26],"routing":[27,65],"in":[28,98,104,110],"network":[29],"applications.":[30],"The":[31],"crossbar":[32],"array":[33],"exhibits":[34],"a":[35,85],"smallest":[36],"cell":[37,99],"size":[38],"of":[39,64,75,116],"16.3F":[40],"<sup":[41],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[42],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[43],"by":[44],"using":[45],"2-diode-2-ReRAM":[46],"(2D2R)":[47],"nvTCAM":[48],"cell,":[49],"useful":[50],"further":[52],"3-dimension":[53],"(3D)":[54],"stacking.":[55],"K-means":[56],"clustering":[57],"employed":[59],"to":[60,84],"allocate":[61],"the":[62,73],"storage":[63],"table":[66],"entry":[67],"given":[69],"bank":[70,114],"count.":[71],"Then":[72],"search":[74,105],"destination":[76],"IP":[77],"address":[78],"can":[79],"be":[80],"classified":[81],"confined":[83],"specific":[86],"bank,":[87],"reducing":[88],"active":[89],"banks":[90],"saving.":[93],"Evaluations":[94],"show":[95],">3X":[96],"improvement":[97],">70%":[102],"reduction":[103],"energy":[106],"limited":[108],"overhead":[109],"silicon":[111],"area":[112],"count":[115],"four.":[117]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}