{"id":"https://openalex.org/W2908401614","doi":"https://doi.org/10.1109/asscc.2018.8579271","title":"A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range","display_name":"A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range","publication_year":2018,"publication_date":"2018-11-01","ids":{"openalex":"https://openalex.org/W2908401614","doi":"https://doi.org/10.1109/asscc.2018.8579271","mag":"2908401614"},"language":"en","primary_location":{"id":"doi:10.1109/asscc.2018.8579271","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asscc.2018.8579271","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100423044","display_name":"Zhao Zhang","orcid":"https://orcid.org/0000-0002-9009-9045"},"institutions":[{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]},{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhao Zhang","raw_affiliation_strings":["State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I4210165038"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110429741","display_name":"Jincheng Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]},{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jincheng Yang","raw_affiliation_strings":["State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I4210165038"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100657035","display_name":"Liyuan Liu","orcid":"https://orcid.org/0000-0003-2585-323X"},"institutions":[{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]},{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liyuan Liu","raw_affiliation_strings":["State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I4210165038"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114831924","display_name":"N. D. Qi","orcid":"https://orcid.org/0000-0002-2267-620X"},"institutions":[{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]},{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Nan Qi","raw_affiliation_strings":["State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I4210165038"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032976671","display_name":"Feng Peng","orcid":"https://orcid.org/0009-0008-5036-460X"},"institutions":[{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]},{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Peng Feng","raw_affiliation_strings":["State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I4210165038"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100414628","display_name":"Jian Liu","orcid":"https://orcid.org/0000-0001-8057-2444"},"institutions":[{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]},{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Liu","raw_affiliation_strings":["State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I4210165038"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110665174","display_name":"Nanjian Wu","orcid":"https://orcid.org/0000-0001-8022-0262"},"institutions":[{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]},{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Nanjian Wu","raw_affiliation_strings":["State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Superlattice and Microstructures Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I4210165038"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5100423044"],"corresponding_institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I4210165038"],"apc_list":null,"apc_paid":null,"fwci":0.3863,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.64935356,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"227","last_page":"230"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.705723226070404},{"id":"https://openalex.org/keywords/wideband","display_name":"Wideband","score":0.6943805813789368},{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.6904940605163574},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.549481987953186},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5480426549911499},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.5201578736305237},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4600541293621063},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45672115683555603},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.43312543630599976},{"id":"https://openalex.org/keywords/phase-frequency-detector","display_name":"Phase frequency detector","score":0.4313865005970001},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25961828231811523},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.23942819237709045},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2179393470287323},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2025810182094574},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.181083083152771},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.10397696495056152},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.09406739473342896}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.705723226070404},{"id":"https://openalex.org/C2780202535","wikidata":"https://www.wikidata.org/wiki/Q4524457","display_name":"Wideband","level":2,"score":0.6943805813789368},{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.6904940605163574},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.549481987953186},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5480426549911499},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.5201578736305237},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4600541293621063},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45672115683555603},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.43312543630599976},{"id":"https://openalex.org/C2776158855","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase frequency detector","level":5,"score":0.4313865005970001},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25961828231811523},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.23942819237709045},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2179393470287323},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2025810182094574},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.181083083152771},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.10397696495056152},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.09406739473342896},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asscc.2018.8579271","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asscc.2018.8579271","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1972768432","https://openalex.org/W2017135263","https://openalex.org/W2121854746","https://openalex.org/W2123266073","https://openalex.org/W2126973480","https://openalex.org/W2160063814","https://openalex.org/W2558930851","https://openalex.org/W2743747137"],"related_works":["https://openalex.org/W2330020385","https://openalex.org/W2351641102","https://openalex.org/W2769299326","https://openalex.org/W2161157531","https://openalex.org/W1518908815","https://openalex.org/W2017031079","https://openalex.org/W2544336511","https://openalex.org/W3027303490","https://openalex.org/W2187761697","https://openalex.org/W3133402311"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,23,28],"fast":[4],"auto":[5],"frequency":[6,16,63,72,103],"calibration":[7],"(AFC)":[8],"technique":[9,53,86],"for":[10],"wideband":[11],"PLL":[12,82],"with":[13,83,120],"wide":[14,71],"reference":[15,62,75,102],"range.":[17],"The":[18,95],"AFC":[19,37,43,50,58,67,85,111,121],"circuit":[20],"block":[21],"adopts":[22,47],"proposed":[24],"clock":[25],"controller":[26],"and":[27,64,89],"current-mode":[29],"logic":[30],"(CML)":[31],"divider-by-2":[32],"divider":[33],"to":[34,54,65,107,117,126],"accelerate":[35],"the":[36,40,48,57,101,110],"process":[38,59],"without":[39],"penalty":[41],"of":[42,74],"resolution.":[44],"It":[45],"also":[46],"adjustable":[49],"counting":[51],"period":[52],"speed":[55],"up":[56],"at":[60],"low":[61],"reduce":[66],"time":[68,112],"variation":[69],"within":[70],"range":[73,104,123],"clock.":[76],"A":[77],"0.1~5":[78],"GHz":[79],"\u0394\u03a3":[80],"fractional-N":[81],"this":[84],"is":[87],"designed":[88],"implemented":[90],"in":[91,100],"65-nm":[92],"CMOS":[93],"process.":[94],"measurement":[96],"results":[97],"show":[98],"that":[99],"from":[105,115,124],"15":[106],"50":[108],"MHz,":[109],"varies":[113],"only":[114],"1.25":[116],"1.86":[118],"\u03bcs":[119],"resolution":[122],"3":[125],"5":[127],"MHz.":[128]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}