{"id":"https://openalex.org/W2779883788","doi":"https://doi.org/10.1109/asscc.2017.8240240","title":"MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage","display_name":"MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage","publication_year":2017,"publication_date":"2017-11-01","ids":{"openalex":"https://openalex.org/W2779883788","doi":"https://doi.org/10.1109/asscc.2017.8240240","mag":"2779883788"},"language":"en","primary_location":{"id":"doi:10.1109/asscc.2017.8240240","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asscc.2017.8240240","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018264265","display_name":"Hikaru Watanabe","orcid":"https://orcid.org/0000-0001-7329-9638"},"institutions":[{"id":"https://openalex.org/I96679780","display_name":"Chuo University","ror":"https://ror.org/03qvqb743","country_code":"JP","type":"education","lineage":["https://openalex.org/I96679780"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Hikaru Watanabe","raw_affiliation_strings":["Department of Electrical, Electronic, and Communication Engineering, Chuo University, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Electronic, and Communication Engineering, Chuo University, Tokyo, Japan","institution_ids":["https://openalex.org/I96679780"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043922603","display_name":"Yoshiaki Deguchi","orcid":"https://orcid.org/0000-0002-1319-4647"},"institutions":[{"id":"https://openalex.org/I96679780","display_name":"Chuo University","ror":"https://ror.org/03qvqb743","country_code":"JP","type":"education","lineage":["https://openalex.org/I96679780"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yoshiaki Deguchi","raw_affiliation_strings":["Department of Electrical, Electronic, and Communication Engineering, Chuo University, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Electronic, and Communication Engineering, Chuo University, Tokyo, Japan","institution_ids":["https://openalex.org/I96679780"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032914719","display_name":"Ken Takeuchi","orcid":"https://orcid.org/0000-0002-9345-6503"},"institutions":[{"id":"https://openalex.org/I96679780","display_name":"Chuo University","ror":"https://ror.org/03qvqb743","country_code":"JP","type":"education","lineage":["https://openalex.org/I96679780"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ken Takeuchi","raw_affiliation_strings":["Department of Electrical, Electronic, and Communication Engineering, Chuo University, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Electronic, and Communication Engineering, Chuo University, Tokyo, Japan","institution_ids":["https://openalex.org/I96679780"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5018264265"],"corresponding_institution_ids":["https://openalex.org/I96679780"],"apc_list":null,"apc_paid":null,"fwci":0.5851,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.76926895,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"157","last_page":"160"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/huffman-coding","display_name":"Huffman coding","score":0.8003121614456177},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7794101238250732},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.7578514814376831},{"id":"https://openalex.org/keywords/flash-file-system","display_name":"Flash file system","score":0.6411112546920776},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5609393119812012},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.520719587802887},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5049052834510803},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.5048680901527405},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4769286513328552},{"id":"https://openalex.org/keywords/computer-data-storage","display_name":"Computer data storage","score":0.4143248200416565},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33888131380081177},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2697610557079315},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.2643470764160156},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.24902307987213135},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21943843364715576},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.17774367332458496}],"concepts":[{"id":"https://openalex.org/C46900642","wikidata":"https://www.wikidata.org/wiki/Q2647","display_name":"Huffman coding","level":3,"score":0.8003121614456177},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7794101238250732},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7578514814376831},{"id":"https://openalex.org/C27670709","wikidata":"https://www.wikidata.org/wiki/Q5457555","display_name":"Flash file system","level":4,"score":0.6411112546920776},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5609393119812012},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.520719587802887},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5049052834510803},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.5048680901527405},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4769286513328552},{"id":"https://openalex.org/C194739806","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Computer data storage","level":2,"score":0.4143248200416565},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33888131380081177},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2697610557079315},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.2643470764160156},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.24902307987213135},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21943843364715576},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.17774367332458496},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asscc.2017.8240240","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asscc.2017.8240240","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1995875735","https://openalex.org/W2060108852","https://openalex.org/W2102646391","https://openalex.org/W2128708426","https://openalex.org/W2742345709"],"related_works":["https://openalex.org/W2108442992","https://openalex.org/W2354277217","https://openalex.org/W1985253609","https://openalex.org/W2363230565","https://openalex.org/W2366317867","https://openalex.org/W2377021172","https://openalex.org/W2356175334","https://openalex.org/W2368621827","https://openalex.org/W2375456104","https://openalex.org/W1925997141"],"abstract_inverted_index":{"Asymmetric":[0],"Error":[1],"Reduction":[2],"Huffman":[3],"Coding":[4],"(AERH)":[5],"is":[6,92],"proposed":[7,72],"for":[8],"MLC/3LC":[9,75],"NAND":[10,55,76,90],"flash":[11,77,91],"memory":[12,27,41],"used":[13],"as":[14],"SSD":[15,86],"cache":[16,87],"in":[17],"the":[18,63,67,81],"tiered":[19],"hierarchical":[20],"storage.":[21],"AERH":[22,43,79],"compresses":[23],"data,":[24],"reduces":[25],"asymmetric":[26],"cell":[28],"errors":[29,46],"by":[30,47],"modulating":[31],"Vth":[32],"distribution":[33],"and":[34,38,49,53,66],"thus":[35],"enhances":[36],"reliability":[37,83],"endurance":[39],"of":[40,51,71,84],"cells.":[42],"decreases":[44],"data-retention":[45],"72.6%":[48],"82.6%":[50],"MLC":[52],"3LC":[54],"flash,":[56],"respectively.":[57],"In":[58],"addition,":[59],"this":[60],"paper":[61],"analyzes":[62],"compression":[64],"ratio":[65],"cost":[68],"(effective":[69],"bits/cell)":[70],"AERH.":[73],"Proposed":[74],"with":[78],"realizes":[80],"utmost":[82],"enterprise":[85],"where":[88],"SLC":[89],"commonly":[93],"used.":[94]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}