{"id":"https://openalex.org/W2244217849","doi":"https://doi.org/10.1109/asscc.2015.7387472","title":"A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy","display_name":"A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2244217849","doi":"https://doi.org/10.1109/asscc.2015.7387472","mag":"2244217849"},"language":"en","primary_location":{"id":"doi:10.1109/asscc.2015.7387472","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asscc.2015.7387472","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104058101","display_name":"Sung-Yong Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Sung-Yong Kim","raw_affiliation_strings":["College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea"],"affiliations":[{"raw_affiliation_string":"College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068295871","display_name":"Xuefan Jin","orcid":"https://orcid.org/0000-0002-2784-4196"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Xuefan Jin","raw_affiliation_strings":["College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea"],"affiliations":[{"raw_affiliation_string":"College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009724263","display_name":"Jung\u2010Hoon Chun","orcid":"https://orcid.org/0000-0002-2668-6739"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jung-Hoon Chun","raw_affiliation_strings":["College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea"],"affiliations":[{"raw_affiliation_string":"College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052707197","display_name":"Kee-Won Kwon","orcid":"https://orcid.org/0000-0003-4513-8532"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kee-Won Kwon","raw_affiliation_strings":["College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea"],"affiliations":[{"raw_affiliation_string":"College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5104058101"],"corresponding_institution_ids":["https://openalex.org/I848706"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.10959966,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"47","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8282508850097656},{"id":"https://openalex.org/keywords/dither","display_name":"Dither","score":0.6521444916725159},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6430432200431824},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.5688443779945374},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.5663378238677979},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5206329226493835},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.5202813744544983},{"id":"https://openalex.org/keywords/discriminator","display_name":"Discriminator","score":0.4505194425582886},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.43136709928512573},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.4279817044734955},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4192425012588501},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.39839136600494385},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.38781261444091797},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.352586567401886},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.3000577688217163},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2229452133178711},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19299697875976562},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1426382064819336},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09185430407524109},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0831657350063324}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8282508850097656},{"id":"https://openalex.org/C70451592","wikidata":"https://www.wikidata.org/wiki/Q376493","display_name":"Dither","level":3,"score":0.6521444916725159},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6430432200431824},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.5688443779945374},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.5663378238677979},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5206329226493835},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.5202813744544983},{"id":"https://openalex.org/C2779803651","wikidata":"https://www.wikidata.org/wiki/Q5282088","display_name":"Discriminator","level":3,"score":0.4505194425582886},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.43136709928512573},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.4279817044734955},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4192425012588501},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.39839136600494385},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.38781261444091797},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.352586567401886},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.3000577688217163},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2229452133178711},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19299697875976562},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1426382064819336},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09185430407524109},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0831657350063324},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asscc.2015.7387472","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asscc.2015.7387472","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6800000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2103011017","https://openalex.org/W2108914577","https://openalex.org/W2126227985","https://openalex.org/W2169622190"],"related_works":["https://openalex.org/W2800982453","https://openalex.org/W2607980137","https://openalex.org/W2019505157","https://openalex.org/W2157266366","https://openalex.org/W1799675054","https://openalex.org/W1989508992","https://openalex.org/W2159517497","https://openalex.org/W2532325543","https://openalex.org/W2533878492","https://openalex.org/W2499069953"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,19,22,29,47,51,62,110],"fully":[4],"digital":[5],"delay":[6],"locked":[7],"loop":[8],"(DLL)":[9],"that":[10],"can":[11],"acquire":[12],"lock":[13,36],"in":[14,37,96],"four":[15,38],"clock":[16,39],"cycles":[17,40],"with":[18,28,41],"resolution":[20,60],"of":[21,87],"1/4":[23,63],"NAND-delay.":[24,43,64],"The":[25,65],"proposed":[26,100],"DLL":[27,101],"multi-dither-free":[30,48],"phase":[31,49,55,76],"detector":[32],"acquires":[33],"the":[34,59,71,75,80,85,92,99],"initial":[35],"1/2":[42],"Then,":[44],"it":[45],"utilizes":[46],"detector,":[50],"region":[52,66],"accumulator,":[53],"and":[54,74,89,105],"blenders,":[56],"to":[57,61],"improve":[58],"accumulator":[67],"which":[68],"continuously":[69],"steers":[70],"control":[72],"registers":[73],"blender,":[77],"adaptively":[78],"controls":[79],"tracking":[81],"bandwidth":[82],"depending":[83],"on":[84],"amount":[86],"jitter,":[88],"effectively":[90],"suppresses":[91],"dithering":[93],"jitter.":[94],"Fabricated":[95],"65nm":[97],"CMOS,":[98],"occupies":[102],"0.0432":[103],"mm2,":[104],"consumes":[106],"3.7":[107],"mW":[108],"from":[109],"1.2-V":[111],"supply":[112],"at":[113],"2":[114],"GHz.":[115]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
