{"id":"https://openalex.org/W4246381373","doi":"https://doi.org/10.1109/aspdac.2018.8297386","title":"SAT-based area recovery in structural technology mapping","display_name":"SAT-based area recovery in structural technology mapping","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W4246381373","doi":"https://doi.org/10.1109/aspdac.2018.8297386"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2018.8297386","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2018.8297386","pdf_url":null,"source":{"id":"https://openalex.org/S4363608266","display_name":"2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/268576","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060087941","display_name":"Bruno Schmitt","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Bruno Schmitt","raw_affiliation_strings":["Ecole Polytechnique Federale de Lausanne (EPFL)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique Federale de Lausanne (EPFL)","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["Department of EECS, UC Berkley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of EECS, UC Berkley","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064568178","display_name":"Robert K. Brayton","orcid":"https://orcid.org/0000-0002-3861-1718"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Robert Brayton","raw_affiliation_strings":["Department of EECS, UC Berkley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of EECS, UC Berkley","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"586","last_page":"591"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8149843215942383},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.6758262515068054},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6227132081985474},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.6096462607383728},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.49533572793006897},{"id":"https://openalex.org/keywords/timer","display_name":"Timer","score":0.4631144106388092},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.46176356077194214},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3795086443424225},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.32465556263923645},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24453243613243103},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.098502516746521}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8149843215942383},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.6758262515068054},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6227132081985474},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.6096462607383728},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.49533572793006897},{"id":"https://openalex.org/C2776633867","wikidata":"https://www.wikidata.org/wiki/Q186612","display_name":"Timer","level":3,"score":0.4631144106388092},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.46176356077194214},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3795086443424225},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.32465556263923645},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24453243613243103},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.098502516746521},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/aspdac.2018.8297386","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2018.8297386","pdf_url":null,"source":{"id":"https://openalex.org/S4363608266","display_name":"2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:268576","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/268576","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"WoS","raw_type":"conference proceedings"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:268576","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/268576","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"WoS","raw_type":"conference proceedings"},"sustainable_development_goals":[{"score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1500127208","https://openalex.org/W1858858479","https://openalex.org/W1900929702","https://openalex.org/W1993932586","https://openalex.org/W2016684773","https://openalex.org/W2017461851","https://openalex.org/W2108508582","https://openalex.org/W2116758077","https://openalex.org/W2299459657","https://openalex.org/W4239323126","https://openalex.org/W6630973549","https://openalex.org/W6639475887"],"related_works":["https://openalex.org/W2136647108","https://openalex.org/W2360439717","https://openalex.org/W2388292776","https://openalex.org/W2765214557","https://openalex.org/W2361181213","https://openalex.org/W2350029007","https://openalex.org/W1965180958","https://openalex.org/W1031622928","https://openalex.org/W2350005463","https://openalex.org/W1973428399"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,20,30,44,57,73,120],"fast":[4],"SAT-based":[5],"algorithm":[6,18],"for":[7,63,106,115],"recovering":[8],"area":[9,92,101,110],"applicable":[10],"to":[11,35],"an":[12,98],"already":[13,69],"technology":[14],"mapped":[15,31,68],"circuit.":[16],"The":[17,78],"considers":[19],"sequence":[21],"of":[22,40,86,103],"relatively":[23],"small":[24],"overlapping":[25],"regions,":[26],"called":[27],"windows,":[28],"in":[29],"network":[32],"and":[33],"tries":[34],"improve":[36],"the":[37,53,89,95,109],"current":[38],"mapping":[39],"each":[41],"window":[42],"using":[43],"SAT":[45,54],"solver.":[46],"Delay":[47],"constraints":[48],"are":[49,61],"considered":[50],"by":[51,72],"interfacing":[52],"solver":[55],"with":[56],"timer.":[58],"Experimental":[59],"results":[60,93],"given":[62],"benchmarks":[64,108],"that":[65],"have":[66],"been":[67],"into":[70],"6-LUTs":[71],"high-effort":[74],"area-only":[75],"synthesis/mapping":[76],"flow.":[77],"new":[79],"mapper":[80],"starting":[81],"from":[82],"these":[83],"results,":[84],"many":[85],"which":[87],"represented":[88],"best":[90],"known":[91],"at":[94],"time,":[96],"achieved":[97],"additional":[99],"average":[100],"reduction":[102,111],"3-4%,":[104],"while":[105],"some":[107],"exceeded":[112],"10%.":[113],"Runtime":[114],"any":[116],"example":[117],"was":[118],"only":[119],"few":[121],"seconds.":[122]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}