{"id":"https://openalex.org/W2295783341","doi":"https://doi.org/10.1109/aspdac.2016.7428038","title":"Routing path reuse maximization for efficient NV-FPGA reconfiguration","display_name":"Routing path reuse maximization for efficient NV-FPGA reconfiguration","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2295783341","doi":"https://doi.org/10.1109/aspdac.2016.7428038","mag":"2295783341"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2016.7428038","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2016.7428038","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000876494","display_name":"Yuan Xue","orcid":"https://orcid.org/0000-0002-5518-165X"},"institutions":[{"id":"https://openalex.org/I86501945","display_name":"University of Delaware","ror":"https://ror.org/01sbq1a82","country_code":"US","type":"education","lineage":["https://openalex.org/I86501945"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yuan Xue","raw_affiliation_strings":["Department of Electrical and Computer Eng., University of Delaware, Newark, DE, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Eng., University of Delaware, Newark, DE, USA","institution_ids":["https://openalex.org/I86501945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084074589","display_name":"Patrick Cronin","orcid":"https://orcid.org/0000-0003-2091-4830"},"institutions":[{"id":"https://openalex.org/I86501945","display_name":"University of Delaware","ror":"https://ror.org/01sbq1a82","country_code":"US","type":"education","lineage":["https://openalex.org/I86501945"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patrick Cronin","raw_affiliation_strings":["Department of Electrical and Computer Eng., University of Delaware, Newark, DE, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Eng., University of Delaware, Newark, DE, USA","institution_ids":["https://openalex.org/I86501945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016268650","display_name":"Chengmo Yang","orcid":"https://orcid.org/0000-0003-0978-1504"},"institutions":[{"id":"https://openalex.org/I86501945","display_name":"University of Delaware","ror":"https://ror.org/01sbq1a82","country_code":"US","type":"education","lineage":["https://openalex.org/I86501945"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chengmo Yang","raw_affiliation_strings":["Department of Electrical and Computer Eng., University of Delaware, Newark, DE, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Eng., University of Delaware, Newark, DE, USA","institution_ids":["https://openalex.org/I86501945"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066534595","display_name":"Jingtong Hu","orcid":"https://orcid.org/0000-0003-4029-4034"},"institutions":[{"id":"https://openalex.org/I115475287","display_name":"Oklahoma State University","ror":"https://ror.org/01g9vbr38","country_code":"US","type":"education","lineage":["https://openalex.org/I115475287"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jingtong Hu","raw_affiliation_strings":["School of Electrical and Computer Eng., Oklahoma State University, Stillwater, OK, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Eng., Oklahoma State University, Stillwater, OK, USA","institution_ids":["https://openalex.org/I115475287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5000876494"],"corresponding_institution_ids":["https://openalex.org/I86501945"],"apc_list":null,"apc_paid":null,"fwci":1.4701,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.83398256,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"360","last_page":"365"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8750865459442139},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7680445909500122},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7625831365585327},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6930604577064514},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.6912961006164551},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6256371736526489},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5937406420707703},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5273585915565491},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5027990341186523},{"id":"https://openalex.org/keywords/maximization","display_name":"Maximization","score":0.48230695724487305},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.45612847805023193},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3637230396270752},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2180401086807251},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20115837454795837},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13070407509803772},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.07386741042137146}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8750865459442139},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7680445909500122},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7625831365585327},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6930604577064514},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.6912961006164551},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6256371736526489},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5937406420707703},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5273585915565491},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5027990341186523},{"id":"https://openalex.org/C2776330181","wikidata":"https://www.wikidata.org/wiki/Q18358244","display_name":"Maximization","level":2,"score":0.48230695724487305},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.45612847805023193},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3637230396270752},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2180401086807251},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20115837454795837},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13070407509803772},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.07386741042137146},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2016.7428038","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2016.7428038","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7200000286102295}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1524957862","https://openalex.org/W1675151442","https://openalex.org/W1830708738","https://openalex.org/W1900357085","https://openalex.org/W1975550397","https://openalex.org/W1977850862","https://openalex.org/W1993200203","https://openalex.org/W2005602803","https://openalex.org/W2016203766","https://openalex.org/W2055567033","https://openalex.org/W2076613578","https://openalex.org/W2085743209","https://openalex.org/W2099798359","https://openalex.org/W2105011467","https://openalex.org/W2105429308","https://openalex.org/W2111865441","https://openalex.org/W2113645429","https://openalex.org/W2133712953","https://openalex.org/W2138840350","https://openalex.org/W2139580250","https://openalex.org/W2152664027","https://openalex.org/W2171051477","https://openalex.org/W2222512263","https://openalex.org/W4234247516","https://openalex.org/W4238154064","https://openalex.org/W4244361616","https://openalex.org/W6638478215","https://openalex.org/W6664142628","https://openalex.org/W6675503236","https://openalex.org/W6675914063","https://openalex.org/W6682424364","https://openalex.org/W7045235261"],"related_works":["https://openalex.org/W2357657342","https://openalex.org/W2153432761","https://openalex.org/W1580144672","https://openalex.org/W2152623100","https://openalex.org/W2142042635","https://openalex.org/W4214878056","https://openalex.org/W4248634784","https://openalex.org/W2103296973","https://openalex.org/W1988127757","https://openalex.org/W2165832238"],"abstract_inverted_index":{"Non-Volatile":[0],"memory-based":[1],"FPGAs":[2,10],"(NV-FPGAs)":[3],"are":[4],"expected":[5],"to":[6,11,103],"replace":[7],"traditional":[8],"SRAM-based":[9],"achieve":[12,104],"higher":[13],"scalability":[14],"and":[15,32,112],"lower":[16],"power":[17],"consumption.":[18],"Yet":[19],"the":[20,37,47,79,82,86,98],"slow":[21],"write":[22],"performance":[23],"of":[24,40,50,69,81],"NVMs":[25],"not":[26],"only":[27],"challenges":[28],"FPGA":[29],"reconfiguration":[30,66],"speed":[31],"overhead":[33],"but":[34],"also":[35],"constrains":[36],"programming":[38],"cycles":[39],"FPGAs.":[41],"To":[42],"efficiently":[43],"configure":[44],"switch":[45],"boxes,":[46],"majority":[48],"component":[49],"an":[51],"FPGA,":[52],"this":[53],"paper":[54],"proposes":[55],"a":[56,64,72],"routing":[57,70,74,121],"path":[58,109],"reuse":[59,110],"technique.":[60],"Technical":[61],"contributions":[62],"include":[63],"mathematical":[65],"cost":[67,119],"model":[68],"resources,":[71],"reuse-aware":[73],"algorithm,":[75],"as":[76,78,105,107,114,116],"well":[77],"incorporation":[80],"proposed":[83,99],"algorithm":[84],"into":[85],"standard":[87,93],"VTR":[88],"CAD":[89],"tool.":[90],"Experiments":[91],"on":[92],"MCNC":[94],"benchmarks":[95],"show":[96],"that":[97],"scheme":[100],"is":[101],"able":[102],"much":[106,115],"40%":[108],"rate":[111],"reduce":[113],"34.0%":[117],"configuration":[118],"for":[120],"resources.":[122]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
