{"id":"https://openalex.org/W2293815340","doi":"https://doi.org/10.1109/aspdac.2016.7428019","title":"A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization","display_name":"A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2293815340","doi":"https://doi.org/10.1109/aspdac.2016.7428019","mag":"2293815340"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2016.7428019","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2016.7428019","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011277985","display_name":"Yuguang Chen","orcid":"https://orcid.org/0000-0003-4520-5395"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yu-Guang Chen","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023481839","display_name":"Wan-Yu Wen","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wan-Yu Wen","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101898077","display_name":"Yunting Wang","orcid":"https://orcid.org/0000-0002-9246-4173"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yun-Ting Wang","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030348624","display_name":"You-Luen Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"You-Luen Lee","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102148020","display_name":"Shih-Chieh Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Chieh Chang","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5011277985"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.3675,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63513675,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"250","last_page":"255"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6046492457389832},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4711032509803772},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45675545930862427},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4229500889778137},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.413695752620697},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3745855689048767},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1508747637271881},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11298850178718567},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.06953096389770508}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6046492457389832},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4711032509803772},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45675545930862427},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4229500889778137},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.413695752620697},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3745855689048767},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1508747637271881},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11298850178718567},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.06953096389770508},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2016.7428019","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2016.7428019","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1567646530","https://openalex.org/W1582019256","https://openalex.org/W1963902051","https://openalex.org/W1983849809","https://openalex.org/W1985018624","https://openalex.org/W2002377960","https://openalex.org/W2008093830","https://openalex.org/W2045294186","https://openalex.org/W2045704975","https://openalex.org/W2059251513","https://openalex.org/W2070152203","https://openalex.org/W2076536455","https://openalex.org/W2091339753","https://openalex.org/W2101293217","https://openalex.org/W2106484393","https://openalex.org/W2111755315","https://openalex.org/W2112102221","https://openalex.org/W2126416778","https://openalex.org/W2136325278","https://openalex.org/W2148780488","https://openalex.org/W2161036704","https://openalex.org/W3147234326","https://openalex.org/W4234974086","https://openalex.org/W6650807564"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W2789349722","https://openalex.org/W1977171228","https://openalex.org/W2102927888","https://openalex.org/W4249951793","https://openalex.org/W2170504327","https://openalex.org/W2150981204"],"abstract_inverted_index":{"Low":[0],"power":[1,19,107,124,147],"design":[2,60],"techniques":[3],"have":[4],"been":[5],"extensively":[6],"applied":[7,30],"in":[8,135],"modern":[9],"IC":[10],"designs":[11,86],"to":[12,53,119,145],"avoid":[13],"negative":[14],"side":[15],"effects":[16],"from":[17,47,73],"high":[18,49],"density.":[20],"Unlike":[21],"Dynamic":[22,67],"Voltage":[23],"and/or":[24],"Frequency":[25],"Scaling":[26],"(DVFS)":[27],"approaches":[28],"only":[29,155],"on":[31],"a":[32,37,48,54,102],"\u201cfixed\u201d":[33],"design,":[34],"we":[35,93],"propose":[36,94],"dynamic":[38,45],"logic":[39,51,57],"reconfigurable":[40],"structure":[41,52,64],"strategy":[42],"which":[43,76,115],"allows":[44],"switching":[46],"speed/power":[50,56],"low":[55,106],"structure.":[58],"A":[59],"with":[61,113,130,150,154],"such":[62],"configurable":[63],"is":[65],"called":[66],"Logic":[68],"Reconfigurable":[69],"Structure":[70],"(DLRS).":[71],"Different":[72],"approximate":[74],"computing":[75],"trades":[77],"off":[78],"between":[79,121],"computation":[80],"accuracy":[81],"and":[82,99,101,123,133],"power,":[83],"our":[84],"DLRS":[85,97,112,131],"maintain":[87],"data":[88],"integrity.":[89],"In":[90],"this":[91],"paper,":[92],"novel":[95],"low-cost":[96],"adders":[98,132],"multipliers,":[100],"comprehensive":[103],"framework":[104],"for":[105],"designs.":[108],"We":[109],"further":[110],"integrate":[111],"DVFS,":[114],"creates":[116],"more":[117],"flexibility":[118],"trade-off":[120],"performance":[122],"consumption.":[125],"Experimental":[126],"results":[127],"show":[128],"that":[129],"multipliers":[134],"three":[136],"indoor":[137],"designs,":[138],"the":[139],"proposed":[140],"method":[141],"can":[142],"achieve":[143],"up":[144],"60.05%":[146],"reduction":[148],"compared":[149],"traditional":[151],"DVFS":[152],"scheme":[153],"6.55%":[156],"area":[157],"overhead.":[158]},"counts_by_year":[{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}