{"id":"https://openalex.org/W2293504197","doi":"https://doi.org/10.1109/aspdac.2016.7427972","title":"An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection","display_name":"An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2293504197","doi":"https://doi.org/10.1109/aspdac.2016.7427972","mag":"2293504197"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2016.7427972","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2016.7427972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040405791","display_name":"Dongsheng Yang","orcid":"https://orcid.org/0000-0002-1808-1908"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Dongsheng Yang","raw_affiliation_strings":["Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074494245","display_name":"Wei Deng","orcid":"https://orcid.org/0000-0002-6323-4539"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Wei Deng","raw_affiliation_strings":["Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032076900","display_name":"Aravind Tharayil Narayanan","orcid":"https://orcid.org/0000-0002-6053-6603"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Aravind Tharayil Narayanan","raw_affiliation_strings":["Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110431996","display_name":"Kengo Nakata","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kengo Nakata","raw_affiliation_strings":["Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050565374","display_name":"Teerachot Siriburanon","orcid":"https://orcid.org/0000-0003-1658-9596"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Teerachot Siriburanon","raw_affiliation_strings":["Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064086312","display_name":"Kenichi Okada","orcid":"https://orcid.org/0000-0002-1082-7672"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenichi Okada","raw_affiliation_strings":["Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111453629","display_name":"Akira Matsuzawa","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akira Matsuzawa","raw_affiliation_strings":["Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5040405791"],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":0.3733,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.64092931,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8570449352264404},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8145134449005127},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6357647776603699},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5332351326942444},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4496800899505615},{"id":"https://openalex.org/keywords/stage","display_name":"Stage (stratigraphy)","score":0.4284884035587311},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.38701319694519043},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3624533712863922},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34041285514831543},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2613399624824524}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8570449352264404},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8145134449005127},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6357647776603699},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5332351326942444},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4496800899505615},{"id":"https://openalex.org/C146357865","wikidata":"https://www.wikidata.org/wiki/Q1123245","display_name":"Stage (stratigraphy)","level":2,"score":0.4284884035587311},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.38701319694519043},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3624533712863922},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34041285514831543},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2613399624824524},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/aspdac.2016.7427972","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2016.7427972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},{"id":"pmh:oai:irdb.nii.ac.jp:00897:0004095475","is_oa":false,"landing_page_url":"http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100702367","pdf_url":null,"source":{"id":"https://openalex.org/S7407056385","display_name":"Institutional Repositories DataBase (IRDB)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I184597095","host_organization_name":"National Institute of Informatics","host_organization_lineage":["https://openalex.org/I184597095"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1975693956","https://openalex.org/W2006427734","https://openalex.org/W2019720625","https://openalex.org/W2147533202","https://openalex.org/W2171297533"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W984417604","https://openalex.org/W2498262093","https://openalex.org/W2139484866","https://openalex.org/W2188779191","https://openalex.org/W3134930219","https://openalex.org/W2967785526","https://openalex.org/W188830667","https://openalex.org/W1605914315","https://openalex.org/W1994021281"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,40,48],"automatic":[4],"place-and-routed":[5],"two-stage":[6],"fractional-N":[7,63],"injection-locked":[8,64],"PLL":[9,65],"(IL-PLL)":[10],"using":[11],"soft":[12],"injection":[13],"technique":[14],"for":[15],"on-chip":[16],"clock":[17],"generation.":[18],"Fabricated":[19],"in":[20],"a":[21,28],"65nm":[22],"CMOS":[23],"process,":[24],"this":[25],"prototype":[26],"demonstrates":[27],"3.6-ps":[29],"integrated":[30],"jitter":[31],"at":[32],"1.5222":[33],"GHz":[34],"and":[35],"consumes":[36],"3mW":[37],"leading":[38],"to":[39],"FoM":[41],"of":[42,50],"-224.6":[43],"dB":[44],"while":[45],"only":[46],"occupying":[47],"area":[49],"0.048":[51],"mm":[52],"<sup":[53],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[54],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[55],".":[56],"It":[57],"realizes":[58],"the":[59],"first":[60],"fully":[61],"synthesized":[62],"up-to-date.":[66]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
