{"id":"https://openalex.org/W2043201574","doi":"https://doi.org/10.1109/aspdac.2015.7059095","title":"GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver","display_name":"GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W2043201574","doi":"https://doi.org/10.1109/aspdac.2015.7059095","mag":"2043201574"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2015.7059095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2015.7059095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 20th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057639889","display_name":"Yan Zhu","orcid":"https://orcid.org/0000-0002-5952-2108"},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yan Zhu","raw_affiliation_strings":["Department of Electrical Engineering, University of California, Riverside, CA, USA","Department of Electrical Engineering, University of California, Riverside, 92521, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]},{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Riverside, 92521, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058844682","display_name":"Sheldon X.-D. Tan","orcid":"https://orcid.org/0000-0003-2119-6869"},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sheldon X.-D. Tan","raw_affiliation_strings":["Department of Electrical Engineering, University of California, Riverside, CA, USA","Department of Electrical Engineering, University of California, Riverside, 92521, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]},{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Riverside, 92521, USA","institution_ids":["https://openalex.org/I103635307"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5057639889"],"corresponding_institution_ids":["https://openalex.org/I103635307"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06351465,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"19","issue":null,"first_page":"719","last_page":"724"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8578593730926514},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8199682235717773},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7601737380027771},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.656863808631897},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.5661035776138306},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5077120065689087},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.41547220945358276},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3730852007865906},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.365667462348938},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3497426509857178},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09144189953804016}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8578593730926514},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8199682235717773},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7601737380027771},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.656863808631897},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.5661035776138306},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5077120065689087},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.41547220945358276},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3730852007865906},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.365667462348938},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3497426509857178},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09144189953804016},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2015.7059095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2015.7059095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 20th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1762731526","https://openalex.org/W1966643957","https://openalex.org/W1972462303","https://openalex.org/W1974413754","https://openalex.org/W1988222220","https://openalex.org/W2079930448","https://openalex.org/W2085606491","https://openalex.org/W2099320289","https://openalex.org/W2123864128","https://openalex.org/W2130886743","https://openalex.org/W2151250761","https://openalex.org/W2152211357","https://openalex.org/W2161672754","https://openalex.org/W2164540960","https://openalex.org/W2167078995","https://openalex.org/W2475714590","https://openalex.org/W3147150317","https://openalex.org/W4233217607","https://openalex.org/W4247202174","https://openalex.org/W6641876848","https://openalex.org/W6663682036"],"related_works":["https://openalex.org/W2056543843","https://openalex.org/W2167527468","https://openalex.org/W2586370661","https://openalex.org/W1604758548","https://openalex.org/W2314053740","https://openalex.org/W2804126825","https://openalex.org/W1549048322","https://openalex.org/W4367553810","https://openalex.org/W2104142636","https://openalex.org/W2960681633"],"abstract_inverted_index":{"In":[0,118],"this":[1],"article,":[2],"we":[3,101],"propose":[4],"a":[5,145],"new":[6,25,74,126,164],"parallel":[7,22,67,116],"matrix":[8,147],"solver,":[9],"which":[10,58],"is":[11,27,76,144],"very":[12,51],"amenable":[13],"for":[14,150,155],"Graphic":[15],"Process":[16],"Unit":[17],"(GPU)":[18],"based":[19,28,77,179],"fine-grain":[20,151],"massively-threaded":[21,66],"computing.":[23],"The":[24,73,141],"method":[26,75,190],"on":[29,78,191],"the":[30,37,79,87,96,125,163,176],"graph-based":[31],"symbolic":[32],"analysis":[33],"technique":[34],"to":[35,107,120],"generate":[36],"computing":[38,68,154],"sequence":[39],"of":[40,44,99,114,172],"determinants":[41],"in":[42,95,122,134],"terms":[43],"determinant":[45,81],"decision":[46,82],"diagrams":[47,83],"(DDDs).":[48],"DDD":[49,123],"represents":[50],"simple":[52,92],"data":[53,56,89,93,105,131],"dependence":[54,94],"and":[55,91,112,137,181],"parallelism,":[57],"can":[59,128,167],"be":[60],"explored":[61],"much":[62],"easier":[63],"by":[64,86],"GPU":[65],"than":[69,183],"existing":[70,133],"LU-based":[71],"methods.":[72],"hierarchical":[80],"(HDDDs).":[84],"Inspired":[85],"inherent":[88],"parallelism":[90,121],"evaluation":[97,113,165,180],"process":[98],"HDDD,":[100],"design":[102],"GPU-amenable":[103],"continuous":[104],"structures":[106],"enable":[108],"fast":[109],"memory":[110],"access":[111],"massive":[115,152],"threads.":[117],"addition":[119],"graph,":[124],"algorithm":[127,143,166],"naturally":[129],"explore":[130],"independence":[132],"Monte":[135],"Carlo":[136],"frequency":[138],"domain":[139],"analysis.":[140],"resulting":[142],"general-purpose":[146],"solver":[148],"suitable":[149],"GPU-based":[153],"any":[156],"circuit":[157],"matrices.":[158],"Experimental":[159],"results":[160],"show":[161],"that":[162],"achieve":[168],"about":[169],"two":[170],"orders":[171],"magnitude":[173],"speedup":[174,185],"over":[175,186],"serial":[177],"CPU":[178],"more":[182],"4\u00d7":[184],"numerical":[187],"SPICE-based":[188],"simulation":[189],"some":[192],"large":[193],"analog":[194],"circuits.":[195]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}