{"id":"https://openalex.org/W1965886179","doi":"https://doi.org/10.1109/aspdac.2015.7059050","title":"Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs","display_name":"Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W1965886179","doi":"https://doi.org/10.1109/aspdac.2015.7059050","mag":"1965886179"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2015.7059050","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2015.7059050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 20th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100723553","display_name":"Juyeon Kim","orcid":"https://orcid.org/0000-0003-0563-8452"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Juyeon Kim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea","School of Electrical and Computer Engineering, Seoul National University, Korea#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea","institution_ids":["https://openalex.org/I139264467"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Seoul National University, Korea#TAB#","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049474875","display_name":"Taewhan Kim","orcid":"https://orcid.org/0000-0002-6114-3772"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taewhan Kim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea","School of Electrical and Computer Engineering, Seoul National University, Korea#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea","institution_ids":["https://openalex.org/I139264467"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Seoul National University, Korea#TAB#","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I139264467"],"apc_list":null,"apc_paid":null,"fwci":1.2048,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.81582186,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"466","last_page":"471"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.8645926713943481},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8427724838256836},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7378663420677185},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7161715030670166},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6846697330474854},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6725155115127563},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6092081665992737},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6063784956932068},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.46708962321281433},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4407449960708618},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3883149027824402},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38824671506881714},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3576233983039856},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3021203875541687},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.2288244366645813},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21064847707748413},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1703197956085205},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.15428835153579712},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14929234981536865},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07870450615882874}],"concepts":[{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.8645926713943481},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8427724838256836},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7378663420677185},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7161715030670166},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6846697330474854},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6725155115127563},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6092081665992737},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6063784956932068},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.46708962321281433},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4407449960708618},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3883149027824402},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38824671506881714},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3576233983039856},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3021203875541687},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2288244366645813},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21064847707748413},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1703197956085205},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.15428835153579712},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14929234981536865},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07870450615882874}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2015.7059050","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2015.7059050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 20th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1490763633","https://openalex.org/W1505590927","https://openalex.org/W1511469799","https://openalex.org/W1558331362","https://openalex.org/W1970984428","https://openalex.org/W1976809982","https://openalex.org/W1982390333","https://openalex.org/W1983206124","https://openalex.org/W1992904457","https://openalex.org/W2002848805","https://openalex.org/W2011778848","https://openalex.org/W2100300233","https://openalex.org/W2110697119","https://openalex.org/W2125187803","https://openalex.org/W2137861476","https://openalex.org/W2142850552","https://openalex.org/W2151306440","https://openalex.org/W2153785506","https://openalex.org/W2155621287","https://openalex.org/W2160653894","https://openalex.org/W2162112388","https://openalex.org/W2169827315","https://openalex.org/W3139757448","https://openalex.org/W3143829947","https://openalex.org/W3145128584","https://openalex.org/W3149731687","https://openalex.org/W4233420466","https://openalex.org/W4234887147","https://openalex.org/W4238470610","https://openalex.org/W6633599133","https://openalex.org/W6682727965","https://openalex.org/W6683853949"],"related_works":["https://openalex.org/W3006003651","https://openalex.org/W2088914741","https://openalex.org/W2133326759","https://openalex.org/W2040807843","https://openalex.org/W4247180033","https://openalex.org/W4249038728","https://openalex.org/W1564063853","https://openalex.org/W2559451387","https://openalex.org/W4230501858","https://openalex.org/W60672686"],"abstract_inverted_index":{"Contrary":[0],"to":[1,47,83],"the":[2,9,27,33,41,49,53,73,92,121,135,139,180,189,193,210,222],"bounded":[3,228],"clock":[4,10,20,29,42,63,75,96,125,199,229],"skew":[5,30,76,97,126,200,230],"scheduling,":[6,77],"which":[7,105],"controls":[8],"signal":[11,37,55],"arrival":[12],"times":[13,43],"of":[14,52,62,79,94,120,123,130,137,141,182,197,212,227],"flip-flops":[15],"(FFs)":[16],"so":[17],"that":[18,175,219],"all":[19],"skews":[21],"are":[22,69,81],"within":[23],"a":[24,45,59],"given":[25],"bound,":[26],"useful":[28,74,95,124,198],"scheduling":[31,98,127,201,231],"exploits":[32],"time":[34],"borrowing":[35],"between":[36],"paths":[38],"by":[39,184,192,214,221],"controlling":[40],"in":[44],"way":[46],"meet":[48],"timing":[50],"constraints":[51],"individual":[54],"paths,":[56],"thus":[57],"enabling":[58],"further":[60],"improvement":[61],"frequency.":[64],"However,":[65],"even":[66],"though":[67],"there":[68],"many":[70],"works":[71],"on":[72,186,216],"most":[78],"them":[80],"targeted":[82],"designs":[84,100,129,203,233],"with":[85,101,134,165,171,204,234],"single":[86],"power":[87,103,132,206,236],"mode.":[88],"This":[89],"work":[90],"addresses":[91],"problem":[93,122],"for":[99,111,128,202,232],"multiple":[102,131,205,235],"modes,":[104,207],"is":[106],"nowadays":[107],"an":[108,117],"essential":[109],"concept":[110],"low-power":[112],"designs.":[113],"Precisely,":[114],"we":[115,149],"propose":[116],"optimal":[118,224],"solution":[119],"modes":[133],"objective":[136],"minimizing":[138],"number":[140,181,211],"adjustable":[142],"delay":[143,159,166],"buffers":[144],"(ADBs)":[145],"used.":[146],"In":[147],"addition,":[148],"solve":[150],"two":[151],"practical":[152],"extensions:":[153],"optimally":[154,162],"allocating":[155,163],"ADBs":[156,164,183,213],"having":[157],"quantized":[158],"values":[160],"and":[161,208],"upper":[167],"bound.":[168],"The":[169],"experiments":[170],"benchmark":[172],"circuits":[173],"show":[174],"our":[176],"proposed":[177],"algorithm":[178],"reduces":[179,209],"14.0%":[185],"average":[187,217],"over":[188,218],"results":[190],"produced":[191,220],"conventional":[194],"ADB":[195,225],"allocation":[196,226],"77.3%":[215],"previous":[223],"modes.":[237]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}