{"id":"https://openalex.org/W2061485512","doi":"https://doi.org/10.1109/aspdac.2015.7059013","title":"Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs","display_name":"Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W2061485512","doi":"https://doi.org/10.1109/aspdac.2015.7059013","mag":"2061485512"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2015.7059013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2015.7059013","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 20th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101967869","display_name":"Subhendu Roy","orcid":"https://orcid.org/0000-0001-8554-563X"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subhendu Roy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, USA","Department of Electrical and Computer Engineering, University of Texas at Austin, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, , USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059471428","display_name":"Mihir Choudhury","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mihir Choudhury","raw_affiliation_strings":["IBM T. J. Watson Research Center, Yorktown Heights, USA","IBM T. J Watson Research Center, Yorktown Heights, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM T. J. Watson Research Center, Yorktown Heights, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM T. J Watson Research Center, Yorktown Heights, USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045722906","display_name":"Ruchir Puri","orcid":"https://orcid.org/0009-0006-8803-7079"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ruchir Puri","raw_affiliation_strings":["IBM T. J. Watson Research Center, Yorktown Heights, USA","IBM T. J Watson Research Center, Yorktown Heights, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM T. J. Watson Research Center, Yorktown Heights, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM T. J Watson Research Center, Yorktown Heights, USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, USA","Department of Electrical and Computer Engineering, University of Texas at Austin, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, , USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"249","last_page":"254"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9046297073364258},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6647511720657349},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6029436588287354},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5760019421577454},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.528426468372345},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.5134114027023315},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46852347254753113},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.44436320662498474},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.44012168049812317},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42350414395332336},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3991866111755371},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2980923652648926},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23203524947166443}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9046297073364258},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6647511720657349},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6029436588287354},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5760019421577454},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.528426468372345},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.5134114027023315},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46852347254753113},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.44436320662498474},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.44012168049812317},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42350414395332336},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3991866111755371},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2980923652648926},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23203524947166443},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2015.7059013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2015.7059013","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 20th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1604826642","https://openalex.org/W1963965124","https://openalex.org/W1979306010","https://openalex.org/W1994560221","https://openalex.org/W1997582549","https://openalex.org/W2054115349","https://openalex.org/W2097414281","https://openalex.org/W2100502052","https://openalex.org/W2131647018","https://openalex.org/W2140854523","https://openalex.org/W2141984024","https://openalex.org/W2143462372","https://openalex.org/W2147847555","https://openalex.org/W2163199256","https://openalex.org/W2167099589","https://openalex.org/W2168543008","https://openalex.org/W2168848751","https://openalex.org/W2179314520","https://openalex.org/W2540581201","https://openalex.org/W4235507382","https://openalex.org/W4250041435","https://openalex.org/W6636304122","https://openalex.org/W6683722355"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W2112595260","https://openalex.org/W2558076308","https://openalex.org/W2162004439","https://openalex.org/W4285082868"],"abstract_inverted_index":{"Adders":[0],"are":[1],"the":[2,10,24,35,45,48,77,80,83],"most":[3],"fundamental":[4],"arithmetic":[5],"units,":[6],"and":[7,54,94,117,161,168,183],"often":[8],"on":[9,47],"timing":[11],"critical":[12],"paths":[13],"of":[14,37,79,82,109,128],"microprocessors.":[15],"Among":[16],"various":[17],"adder":[18,153],"configurations,":[19],"parallel":[20,39,73],"prefix":[21,40,74,84],"structures":[22],"provide":[23],"high":[25],"performance":[26,36,157],"adders":[27,75,178],"for":[28,112],"higher":[29],"bit-widths.":[30],"With":[31],"aggressive":[32],"technology":[33,166,181],"scaling,":[34],"a":[38,66,107,131],"adder,":[41],"in":[42,124,156,164,185],"addition":[43],"to":[44,69],"dependence":[46],"logic-level,":[49],"is":[50],"determined":[51],"by":[52,60,103],"wire-length":[53],"congestion":[55],"which":[56],"can":[57,121],"be":[58,122],"mitigated":[59],"adjusting":[61],"fan-out.":[62],"This":[63],"paper":[64],"proposes":[65],"polynomial-time":[67],"algorithm":[68,105],"synthesize":[70],"n":[71,91],"bit":[72,175],"targeting":[76,179],"minimization":[78],"size":[81],"graph":[85],"with":[86],"log":[87],"<sub":[88],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[89],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sub>":[90],"logic":[92],"level":[93],"any":[95],"arbitrary":[96],"fan-out":[97],"restriction.":[98],"The":[99],"design":[100],"space":[101],"exploration":[102],"our":[104,142],"provides":[106],"set":[108],"Pareto-optimal":[110,119],"solutions":[111,120],"delay":[113],"vs.":[114],"power":[115,162],"trade-off,":[116],"these":[118],"used":[123],"high-performance":[125,188],"designs":[126],"instead":[127],"picking":[129],"from":[130],"fixed":[132],"library":[133,182],"(Kogge":[134],"Stone,":[135],"Sklansky":[136],"etc.).":[137],"Experimental":[138],"results":[139],"demonstrate":[140],"that":[141],"approach":[143],"(i)":[144],"excels":[145],"highly":[146],"competitive":[147],"industry":[148],"standard":[149],"Synopsys":[150],"Design":[151],"Compiler":[152],"(128":[154],"bit)":[155],"(2%),":[158],"area":[159],"(25%)":[160],"(13.3%)":[163],"32nm":[165],"node,":[167],"(ii)":[169],"improves":[170],"performance/area":[171],"over":[172],"even":[173],"64":[174],"custom":[176],"designed":[177],"22nm":[180],"implemented":[184],"an":[186],"industrial":[187],"design.":[189]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}