{"id":"https://openalex.org/W2081804337","doi":"https://doi.org/10.1109/aspdac.2014.6742933","title":"Time-domain performance bound analysis for analog and interconnect circuits considering process variations","display_name":"Time-domain performance bound analysis for analog and interconnect circuits considering process variations","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W2081804337","doi":"https://doi.org/10.1109/aspdac.2014.6742933","mag":"2081804337"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2014.6742933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2014.6742933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052859908","display_name":"Tan Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Tan Yu","raw_affiliation_strings":["Dept. Electrical Engineering, University of California, Riverside, CA","Dept. Electr. Eng., Univ. of California, Riverside, Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. Electrical Engineering, University of California, Riverside, CA","institution_ids":["https://openalex.org/I103635307"]},{"raw_affiliation_string":"Dept. Electr. Eng., Univ. of California, Riverside, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058844682","display_name":"Sheldon X.-D. Tan","orcid":"https://orcid.org/0000-0003-2119-6869"},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sheldon X.-D. Tan","raw_affiliation_strings":["Dept. Electrical Engineering, University of California, Riverside, CA","Dept. Electr. Eng., Univ. of California, Riverside, Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. Electrical Engineering, University of California, Riverside, CA","institution_ids":["https://openalex.org/I103635307"]},{"raw_affiliation_string":"Dept. Electr. Eng., Univ. of California, Riverside, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111983610","display_name":"Yici Cai","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yici Cai","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, China","Dept. of Computer Science & Technology, Tsinghua University, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Dept. of Computer Science & Technology, Tsinghua University, Beijing, China#TAB#","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081672763","display_name":"Tang Pu-ying","orcid":null},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Puying Tang","raw_affiliation_strings":["School of Optoelectronic Information, University of Electronic-Science and Technology of China, Chengdu, China","Sch. of Optoelectron. Inf., Univ. of Electron. Sci. & Technol. of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"School of Optoelectronic Information, University of Electronic-Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]},{"raw_affiliation_string":"Sch. of Optoelectron. Inf., Univ. of Electron. Sci. & Technol. of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5052859908"],"corresponding_institution_ids":["https://openalex.org/I103635307"],"apc_list":null,"apc_paid":null,"fwci":0.2093,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.60507847,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"14","issue":null,"first_page":"455","last_page":"460"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6503956913948059},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6223512887954712},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.546665370464325},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5273317098617554},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5010569095611572},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.49305078387260437},{"id":"https://openalex.org/keywords/time-domain","display_name":"Time domain","score":0.4875182807445526},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.48504751920700073},{"id":"https://openalex.org/keywords/modified-nodal-analysis","display_name":"Modified nodal analysis","score":0.48195716738700867},{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.4509418308734894},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4406380355358124},{"id":"https://openalex.org/keywords/network-analysis","display_name":"Network analysis","score":0.42391282320022583},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.41978126764297485},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40952056646347046},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2635394334793091},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.16828498244285583},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11183479428291321},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.100975900888443},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10082346200942993},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09138429164886475}],"concepts":[{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6503956913948059},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6223512887954712},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.546665370464325},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5273317098617554},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5010569095611572},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.49305078387260437},{"id":"https://openalex.org/C103824480","wikidata":"https://www.wikidata.org/wiki/Q185889","display_name":"Time domain","level":2,"score":0.4875182807445526},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.48504751920700073},{"id":"https://openalex.org/C60643732","wikidata":"https://www.wikidata.org/wiki/Q6889414","display_name":"Modified nodal analysis","level":3,"score":0.48195716738700867},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.4509418308734894},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4406380355358124},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.42391282320022583},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.41978126764297485},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40952056646347046},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2635394334793091},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.16828498244285583},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11183479428291321},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.100975900888443},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10082346200942993},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09138429164886475},{"id":"https://openalex.org/C83330619","wikidata":"https://www.wikidata.org/wiki/Q21124872","display_name":"NODAL","level":2,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C105702510","wikidata":"https://www.wikidata.org/wiki/Q514","display_name":"Anatomy","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2014.6742933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2014.6742933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W565193474","https://openalex.org/W1995639759","https://openalex.org/W2004200975","https://openalex.org/W2019942829","https://openalex.org/W2022144657","https://openalex.org/W2030132941","https://openalex.org/W2030999551","https://openalex.org/W2032733423","https://openalex.org/W2038904236","https://openalex.org/W2046057447","https://openalex.org/W2051243171","https://openalex.org/W2116394695","https://openalex.org/W2122691518","https://openalex.org/W2141274564","https://openalex.org/W2143802986","https://openalex.org/W2159254831","https://openalex.org/W2164540960","https://openalex.org/W2165680786","https://openalex.org/W2167165805","https://openalex.org/W3149202397","https://openalex.org/W4229739412","https://openalex.org/W4238484605","https://openalex.org/W6662328799","https://openalex.org/W6663221386","https://openalex.org/W6684207204"],"related_works":["https://openalex.org/W2359005373","https://openalex.org/W2067189296","https://openalex.org/W2095114068","https://openalex.org/W2139030761","https://openalex.org/W2350611166","https://openalex.org/W1603142061","https://openalex.org/W1503325092","https://openalex.org/W2296682797","https://openalex.org/W2443453557","https://openalex.org/W3151822701"],"abstract_inverted_index":{"Time-Domain":[0],"worst":[1],"case":[2],"or":[3],"performance":[4,40,86,112],"bound":[5,41,114],"estimation":[6],"for":[7,16,170],"analog":[8,18,69,98,201],"integrated":[9],"circuits":[10,13,72,101,202,205],"and":[11,19,23,70,99,132,203],"interconnect":[12,71,100,204],"are":[14,102,119],"crucial":[15],"both":[17],"digital":[20],"circuit":[21,65,94,134],"design":[22],"optimization":[24,125],"in":[25,44,87],"the":[26,55,64,80,84,93,129,139,145,149,152,157,164,176,183,193],"presence":[27],"of":[28,51,63,67,83,89,92,96,115,189],"process":[29,126],"variations.":[30],"In":[31],"this":[32],"paper,":[33],"we":[34],"present":[35],"a":[36,74,105,122],"novel":[37],"non-Monte-Carlo":[38],"(MC)":[39],"analysis":[42,60,108],"technique":[43],"time":[45,75,117,141],"domain.":[46],"The":[47],"new":[48,184],"method":[49,166,185],"consists":[50],"several":[52],"steps.":[53],"First":[54],"symbolic":[56,107],"transient":[57],"modified":[58],"nodal":[59],"(MNA)":[61],"formulation":[62],"matrices":[66,95],"(linearized)":[68,97],"at":[73],"step":[76,118],"is":[77,167],"formed.":[78],"Then":[79,110],"closed-form":[81],"expressions":[82],"interested":[85],"terms":[88],"variational":[90,133],"parameters":[91],"derived":[103],"via":[104],"graph-based":[106],"method.":[109,178],"time-domain":[111],"response":[113],"current":[116],"obtained":[120],"by":[121,148,156],"nonlinear":[123],"constrained":[124],"subject":[127],"to":[128],"parameter":[130],"variations":[131],"state":[135],"bounds":[136,146,155,174],"computed":[137,147],"from":[138],"previous":[140],"step.":[142],"We":[143],"study":[144],"proposed":[150,165],"against":[151],"different":[153],"sigma":[154,173],"standard":[158,194],"MC":[159,177],"method,":[160],"which":[161],"shows":[162],"that":[163,182],"more":[168],"efficient":[169],"computing":[171],"high":[172,207],"than":[175],"Experimental":[179],"results":[180],"show":[181],"can":[186],"deliver":[187],"order":[188],"magnitudes":[190],"speedup":[191],"over":[192],"Monte":[195],"Carlo":[196],"simulation":[197],"on":[198],"some":[199],"typical":[200],"with":[206],"accuracy.":[208]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
