{"id":"https://openalex.org/W1973646109","doi":"https://doi.org/10.1109/aspdac.2014.6742885","title":"2-SAT based linear time optimum two-domain clock skew scheduling","display_name":"2-SAT based linear time optimum two-domain clock skew scheduling","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W1973646109","doi":"https://doi.org/10.1109/aspdac.2014.6742885","mag":"1973646109"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2014.6742885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2014.6742885","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020327745","display_name":"Yukihide Kohira","orcid":"https://orcid.org/0000-0002-4063-2497"},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Yukihide Kohira","raw_affiliation_strings":["School of Computer Science and Engineering, The University of Aizu, Japan","School of Computer Science and Engineering, University of Aizu, Aizu-wakamatsu, Japan"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, The University of Aizu, Japan","institution_ids":["https://openalex.org/I141591182"]},{"raw_affiliation_string":"School of Computer Science and Engineering, University of Aizu, Aizu-wakamatsu, Japan","institution_ids":["https://openalex.org/I141591182"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100710412","display_name":"Atsushi Takahashi","orcid":"https://orcid.org/0000-0003-3821-5325"},"institutions":[{"id":"https://openalex.org/I90023481","display_name":"National Institute of Information and Communications Technology","ror":"https://ror.org/016bgq349","country_code":"JP","type":"facility","lineage":["https://openalex.org/I90023481"]},{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsushi Takahashi","raw_affiliation_strings":["Dept. of Communications and Computer Engineering, Tokyo Institute of Technology, Japan","Dept. of Commun. & Comput. Eng., Tokyo Inst. of Technol., Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. of Communications and Computer Engineering, Tokyo Institute of Technology, Japan","institution_ids":["https://openalex.org/I90023481","https://openalex.org/I114531698"]},{"raw_affiliation_string":"Dept. of Commun. & Comput. Eng., Tokyo Inst. of Technol., Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5020327745"],"corresponding_institution_ids":["https://openalex.org/I141591182"],"apc_list":null,"apc_paid":null,"fwci":0.9194,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.7360298,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"173","last_page":"178"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8481841087341309},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.8422142267227173},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.8048043251037598},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7782527804374695},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6885790824890137},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6125147342681885},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6003034710884094},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5356589555740356},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5137806534767151},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5136013031005859},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5051024556159973},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4877263009548187},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4699074625968933},{"id":"https://openalex.org/keywords/time-domain","display_name":"Time domain","score":0.4524494409561157},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.42296847701072693},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4215260148048401},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3789612948894501},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.34087419509887695},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3205171823501587},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18426799774169922},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.1643269956111908},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1551627218723297},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11735612154006958},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07140469551086426},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.06490325927734375}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8481841087341309},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.8422142267227173},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.8048043251037598},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7782527804374695},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6885790824890137},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6125147342681885},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6003034710884094},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5356589555740356},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5137806534767151},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5136013031005859},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5051024556159973},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4877263009548187},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4699074625968933},{"id":"https://openalex.org/C103824480","wikidata":"https://www.wikidata.org/wiki/Q185889","display_name":"Time domain","level":2,"score":0.4524494409561157},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.42296847701072693},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4215260148048401},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3789612948894501},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.34087419509887695},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3205171823501587},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18426799774169922},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.1643269956111908},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1551627218723297},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11735612154006958},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07140469551086426},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.06490325927734375},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2014.6742885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2014.6742885","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1511469799","https://openalex.org/W1530705060","https://openalex.org/W1930768720","https://openalex.org/W1975596503","https://openalex.org/W2011778848","https://openalex.org/W2031823362","https://openalex.org/W2100928338","https://openalex.org/W2113367047","https://openalex.org/W2135347849","https://openalex.org/W2149116320","https://openalex.org/W2163318442","https://openalex.org/W3141997571","https://openalex.org/W4231706861","https://openalex.org/W6631680385"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W2040807843","https://openalex.org/W3006003651","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W4249038728","https://openalex.org/W2174922170","https://openalex.org/W2133326759","https://openalex.org/W2617666058","https://openalex.org/W2127892766"],"abstract_inverted_index":{"Multi-domain":[0],"clock":[1,18,35,40,54,71],"skew":[2,41,72],"scheduling":[3],"is":[4,74],"an":[5,68],"effective":[6],"technique":[7],"to":[8],"improve":[9],"the":[10,22,32,43,46,51],"performance":[11,26,47],"of":[12,25,27,34,45,53],"sequential":[13],"circuits":[14,81,88],"by":[15,92],"using":[16],"practical":[17],"distribution":[19,55],"network.":[20],"Although":[21],"upper":[23],"bound":[24],"a":[28,62],"circuit":[29],"increases":[30,37,57],"as":[31],"number":[33],"domains":[36],"in":[38,95],"multi-domain":[39],"scheduling,":[42],"improvement":[44],"becomes":[48],"smaller":[49],"while":[50],"cost":[52],"network":[56],"much.":[58],"In":[59],"this":[60],"paper,":[61],"linear":[63],"time":[64],"algorithm":[65],"that":[66,86],"finds":[67],"optimum":[69,87],"two-domain":[70],"schedule":[73],"proposed.":[75],"Experimental":[76],"results":[77],"on":[78],"ISCAS89":[79],"benchmark":[80],"and":[82],"artificial":[83],"data":[84],"show":[85],"are":[89],"efficiently":[90],"obtained":[91],"our":[93],"method":[94],"short":[96],"time.":[97]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}