{"id":"https://openalex.org/W2145030123","doi":"https://doi.org/10.1109/aspdac.2014.6742868","title":"Prefetching techniques for STT-RAM based last-level cache in CMP systems","display_name":"Prefetching techniques for STT-RAM based last-level cache in CMP systems","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W2145030123","doi":"https://doi.org/10.1109/aspdac.2014.6742868","mag":"2145030123"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2014.6742868","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2014.6742868","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005196528","display_name":"Mengjie Mao","orcid":null},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mengjie Mao","raw_affiliation_strings":["University of Pittsburgh, Pittsburgh, PA, USA","University of Pittsburgh, Pittsburgh, Pa., USA\u2020\u2020\u2020"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"University of Pittsburgh, Pittsburgh, Pa., USA\u2020\u2020\u2020","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101850376","display_name":"Guangyu Sun","orcid":"https://orcid.org/0000-0001-6436-0820"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guangyu Sun","raw_affiliation_strings":["CECA, Peking University","CECA, Peking University, Beijing, China#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CECA, Peking University","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"CECA, Peking University, Beijing, China#TAB#","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100355339","display_name":"Yong Li","orcid":"https://orcid.org/0000-0002-1183-5359"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yong Li","raw_affiliation_strings":["University of Pittsburgh, Pittsburgh, PA, USA","University of Pittsburgh, Pittsburgh, Pa., USA\u2020\u2020\u2020"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"University of Pittsburgh, Pittsburgh, Pa., USA\u2020\u2020\u2020","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030875484","display_name":"Alex K. Jones","orcid":"https://orcid.org/0000-0001-7498-0206"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alex K. Jones","raw_affiliation_strings":["University of Pittsburgh, Pittsburgh, PA, USA","University of Pittsburgh, Pittsburgh, Pa., USA\u2020\u2020\u2020"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"University of Pittsburgh, Pittsburgh, Pa., USA\u2020\u2020\u2020","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058073627","display_name":"Yiran Chen","orcid":"https://orcid.org/0000-0002-1486-8412"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yiran Chen","raw_affiliation_strings":["University of Pittsburgh, Pittsburgh, PA, USA","University of Pittsburgh, Pittsburgh, Pa., USA\u2020\u2020\u2020"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"University of Pittsburgh, Pittsburgh, Pa., USA\u2020\u2020\u2020","institution_ids":["https://openalex.org/I170201317"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"31","issue":null,"first_page":"67","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.8959486484527588},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8070167899131775},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6732988357543945},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5248710513114929},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.49991393089294434},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.48681995272636414},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.46028628945350647},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44928431510925293},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.43075430393218994},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.41487106680870056},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38077738881111145},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3272864818572998},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.2514990568161011},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24535560607910156},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.16077670454978943}],"concepts":[{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.8959486484527588},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8070167899131775},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6732988357543945},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5248710513114929},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.49991393089294434},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.48681995272636414},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.46028628945350647},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44928431510925293},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.43075430393218994},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.41487106680870056},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38077738881111145},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3272864818572998},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.2514990568161011},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24535560607910156},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.16077670454978943},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2014.6742868","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2014.6742868","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W2010202670","https://openalex.org/W2039633055","https://openalex.org/W2058578697","https://openalex.org/W2064977311","https://openalex.org/W2084007230","https://openalex.org/W2099815586","https://openalex.org/W2100799944","https://openalex.org/W2120246901","https://openalex.org/W2129381159","https://openalex.org/W2135675903","https://openalex.org/W2148831941","https://openalex.org/W2150143212","https://openalex.org/W2152659795","https://openalex.org/W2166620913","https://openalex.org/W2169190816","https://openalex.org/W2543205889","https://openalex.org/W2916411819","https://openalex.org/W3112784795","https://openalex.org/W3145579537","https://openalex.org/W6652940909","https://openalex.org/W6675446712"],"related_works":["https://openalex.org/W1530597339","https://openalex.org/W2336226224","https://openalex.org/W4247641071","https://openalex.org/W4233319313","https://openalex.org/W1937206256","https://openalex.org/W2553481723","https://openalex.org/W4287252510","https://openalex.org/W2145669355","https://openalex.org/W1578001114","https://openalex.org/W2166121368"],"abstract_inverted_index":{"Prefetching":[0],"is":[1],"widely":[2],"used":[3],"in":[4,21,33,76,112],"modern":[5],"computer":[6],"systems":[7],"to":[8,51,67,123],"mitigate":[9],"the":[10,27,34,38,52,69,124],"impact":[11],"of":[12,29,72],"long":[13,53],"memory":[14,22,35,44],"access":[15,43,55],"latency":[16],"by":[17,95],"paying":[18],"extra":[19],"cost":[20],"and":[23,85,107],"cache":[24,48],"accesses.":[25],"However,":[26],"efficacy":[28,71],"prefetching":[30,70],"significantly":[31],"degrades":[32],"hierarchy":[36],"using":[37],"emerging":[39],"spin-transfer":[40],"torque":[41],"random":[42],"(STT-RAM)":[45],"as":[46],"last-level":[47],"(LLC)":[49],"due":[50],"write":[54],"latency.":[56],"In":[57],"this":[58],"work,":[59],"we":[60,100],"propose":[61],"two":[62,98],"orthogonal":[63],"but":[64],"complimentary":[65],"techniques":[66],"improve":[68],"STT-RAM":[73,119],"based":[74,120],"LLC":[75,109],"chip":[77],"multi-processor":[78],"(CMP)":[79],"systems,":[80],"namely,":[81],"request":[82],"prioritization":[83],"(RP)":[84],"hybrid":[86],"local-global":[87],"prefetch":[88],"control":[89],"(HLGPC).":[90],"Simulation":[91],"results":[92],"show":[93],"that":[94],"combining":[96],"these":[97],"techniques,":[99],"can":[101],"achieve":[102],"6.5%~11%":[103],"system":[104,115,125],"performance":[105],"improvement":[106],"4.8%~7.3%":[108],"energy":[110],"saving":[111],"a":[113,117],"quadcore":[114],"with":[116,126],"2MB~8MB":[118],"LLC,":[121],"compared":[122],"only":[127],"basic":[128],"prefetching.":[129]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
