{"id":"https://openalex.org/W2064648717","doi":"https://doi.org/10.1109/aspdac.2014.6742865","title":"Lithographic defect aware placement using compact standard Cells without inter-cell margin","display_name":"Lithographic defect aware placement using compact standard Cells without inter-cell margin","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W2064648717","doi":"https://doi.org/10.1109/aspdac.2014.6742865","mag":"2064648717"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2014.6742865","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2014.6742865","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101738108","display_name":"Seongbo Shim","orcid":"https://orcid.org/0000-0001-5864-3111"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Seongbo Shim","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, Korea","Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069055905","display_name":"Yoojong Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yoojong Lee","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, Korea","Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, Korea","Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101738108"],"corresponding_institution_ids":["https://openalex.org/I157485424"],"apc_list":null,"apc_paid":null,"fwci":0.4187,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68336758,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"220","issue":null,"first_page":"47","last_page":"52"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.8472557067871094},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5985590219497681},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5798853635787964},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5267079472541809},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5248844027519226},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4836336374282837},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.43836015462875366},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42687612771987915},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3222058117389679},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.24474287033081055},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.21832868456840515},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17030835151672363},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.16985538601875305},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.10931316018104553}],"concepts":[{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.8472557067871094},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5985590219497681},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5798853635787964},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5267079472541809},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5248844027519226},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4836336374282837},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.43836015462875366},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42687612771987915},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3222058117389679},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.24474287033081055},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.21832868456840515},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17030835151672363},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.16985538601875305},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.10931316018104553},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2014.6742865","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2014.6742865","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1495417430","https://openalex.org/W1594489858","https://openalex.org/W1968152850","https://openalex.org/W1980367469","https://openalex.org/W1997437921","https://openalex.org/W2001123757","https://openalex.org/W2024060531","https://openalex.org/W2091816381","https://openalex.org/W2120985183","https://openalex.org/W2157255030","https://openalex.org/W2168300107","https://openalex.org/W6642633016","https://openalex.org/W6645378512"],"related_works":["https://openalex.org/W2503825388","https://openalex.org/W2542137666","https://openalex.org/W2120985183","https://openalex.org/W2479684317","https://openalex.org/W2105062779","https://openalex.org/W4200577934","https://openalex.org/W2011535099","https://openalex.org/W2313633487","https://openalex.org/W2024392966","https://openalex.org/W2066616140"],"abstract_inverted_index":{"Conventional":[0],"standard":[1,59,79],"cells":[2,60],"contain":[3],"extra":[4],"space,":[5],"called":[6],"inter-cell":[7,62],"margin,":[8],"to":[9,111],"prevent":[10],"potential":[11],"defects":[12,38],"caused":[13],"by":[14,112,124,158],"lithography":[15],"process.":[16],"Margin":[17],"is":[18,72,84,92,109],"indeed":[19],"necessary":[20],"between":[21],"some":[22],"cell":[23,31,100,119,129],"pairs,":[24],"but":[25],"there":[26],"are":[27,48],"also":[28,85],"lots":[29],"of":[30,44,95,98,136],"pairs":[32,101,120],"that":[33,69,108],"do":[34],"not":[35],"yield":[36],"any":[37],"(or":[39],"have":[40],"very":[41],"low":[42],"probability":[43,71,138,167],"defects)":[45],"when":[46],"they":[47],"placed":[49],"without":[50,61],"margin.":[51,63],"We":[52,115],"address":[53],"a":[54,106,113,147],"new":[55],"placement":[56,142],"problem":[57],"using":[58,151],"Placement":[64],"should":[65],"be":[66,122],"done":[67],"such":[68,81],"defect":[70,96,137,166],"made":[73],"as":[74,76,82,105],"small":[75],"possible":[77],"while":[78],"objectives":[80],"wirelength":[83],"pursued.":[86],"The":[87,140],"key":[88],"in":[89],"this":[90],"approach":[91],"efficient":[93],"computation":[94],"probabilities":[97],"all":[99],"and":[102,164,171],"arranging":[103],"them":[104],"table":[107],"referred":[110],"placer.":[114],"study":[116],"how":[117],"the":[118,134],"can":[121],"grouped":[123],"examining":[125],"similar":[126],"patterns":[127],"along":[128],"boundary,":[130],"which":[131],"greatly":[132],"reduces":[133],"number":[135],"computation.":[139],"proposed":[141],"method":[143],"was":[144,156],"evaluated":[145],"on":[146,160],"few":[148],"test":[149],"circuits":[150],"28-nm":[152],"technology.":[153],"Chip":[154],"area":[155],"reduced":[157],"10.8%":[159],"average":[161,163],"with":[162],"maximum":[165],"kept":[168],"below":[169],"0.4%":[170],"4.1%,":[172],"respectively.":[173]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}