{"id":"https://openalex.org/W2084716321","doi":"https://doi.org/10.1109/aspdac.2013.6509657","title":"SMYLE OpenCL: A programming framework for embedded many-core SoCs","display_name":"SMYLE OpenCL: A programming framework for embedded many-core SoCs","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W2084716321","doi":"https://doi.org/10.1109/aspdac.2013.6509657","mag":"2084716321"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2013.6509657","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2013.6509657","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000257232","display_name":"Hiroyuki Tomiyama","orcid":"https://orcid.org/0000-0003-1655-7877"},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"H. Tomiyama","raw_affiliation_strings":["Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011753705","display_name":"Takuji Hieda","orcid":null},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Hieda","raw_affiliation_strings":["Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110165652","display_name":"Naoki Nishiyama","orcid":null},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"N. Nishiyama","raw_affiliation_strings":["Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000099162","display_name":"Noriko Etani","orcid":null},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"N. Etani","raw_affiliation_strings":["Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050838950","display_name":"Ittetsu Taniguchi","orcid":"https://orcid.org/0000-0002-7843-5907"},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"I. Taniguchi","raw_affiliation_strings":["Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan","institution_ids":["https://openalex.org/I135768898"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5000257232"],"corresponding_institution_ids":["https://openalex.org/I135768898"],"apc_list":null,"apc_paid":null,"fwci":1.2608,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.80974913,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"565","last_page":"567"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8777652978897095},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.685797393321991},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6730605363845825},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6403545141220093},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5743290185928345},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4981265068054199},{"id":"https://openalex.org/keywords/server","display_name":"Server","score":0.44784465432167053},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.4412236511707306},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4310492277145386},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4156586527824402},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40945714712142944},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3609790503978729},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.28372615575790405}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8777652978897095},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.685797393321991},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6730605363845825},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6403545141220093},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5743290185928345},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4981265068054199},{"id":"https://openalex.org/C93996380","wikidata":"https://www.wikidata.org/wiki/Q44127","display_name":"Server","level":2,"score":0.44784465432167053},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.4412236511707306},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4310492277145386},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4156586527824402},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40945714712142944},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3609790503978729},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.28372615575790405},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2013.6509657","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2013.6509657","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6800000071525574,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1516142763","https://openalex.org/W1973757679","https://openalex.org/W2044957017","https://openalex.org/W2063077801","https://openalex.org/W6666466946"],"related_works":["https://openalex.org/W2025467172","https://openalex.org/W4255057712","https://openalex.org/W4251458280","https://openalex.org/W2512412909","https://openalex.org/W1547865754","https://openalex.org/W2126398188","https://openalex.org/W2116570023","https://openalex.org/W4210605172","https://openalex.org/W4245707462","https://openalex.org/W4248999141"],"abstract_inverted_index":{"Embedded":[0],"SoC":[1],"architecture":[2,111],"has":[3],"shifted":[4],"from":[5],"single-core":[6],"to":[7,17,62],"multi/many-core":[8,83],"paradigm":[9],"because":[10,66],"of":[11,23,36,46,67],"better":[12],"power/performance":[13,21],"efficiency.":[14],"In":[15,72],"order":[16],"exploit":[18],"the":[19,24,37,44,55,68,89],"potential":[20],"efficiency":[22],"many-core":[25],"architecture,":[26],"a":[27,77,109,113],"parallel":[28,40],"computing":[29,41,48],"framework":[30,80,87],"is":[31,34],"necessary.":[32],"OpenCL":[33,57,79,86,123],"one":[35],"most":[38],"popular":[39],"frameworks":[42],"in":[43,116],"field":[45],"general-purpose":[47],"on":[49,103],"GPUs":[50],"and":[51,96],"multicore":[52],"servers.":[53],"However,":[54],"existing":[56,122],"implementations":[58],"are":[59],"not":[60],"suitable":[61],"embedded":[63,82],"real-time":[64],"systems":[65],"large":[69],"runtime":[70,90,117],"overhead.":[71],"this":[73],"paper,":[74],"we":[75],"describe":[76],"lightweight":[78],"for":[81],"SoCs.":[84],"Our":[85],"minimizes":[88],"overhead":[91,118],"by":[92],"statically":[93],"creating":[94],"threads":[95],"mapping":[97],"them":[98],"onto":[99],"cores.":[100],"Preliminary":[101],"experiments":[102],"an":[104,121],"FPGA":[105],"prototype":[106],"board":[107],"with":[108,120],"five-core":[110],"shows":[112],"significant":[114],"reduction":[115],"compared":[119],"framework.":[124]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}