{"id":"https://openalex.org/W1969859981","doi":"https://doi.org/10.1109/aspdac.2013.6509636","title":"Optimizing routability in large-scale mixed-size placement","display_name":"Optimizing routability in large-scale mixed-size placement","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W1969859981","doi":"https://doi.org/10.1109/aspdac.2013.6509636","mag":"1969859981"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2013.6509636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2013.6509636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016776689","display_name":"Jason Cong","orcid":"https://orcid.org/0000-0003-2887-6963"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Cong","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, USA","Computer Science Department, University of California, Los Angeles, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023468643","display_name":"Guojie Luo","orcid":"https://orcid.org/0000-0003-4932-3655"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guojie Luo","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Peking University, Beijing, China","[Sch. of Electr. Eng. & Comput. Sci., Peking Univ., Beijing, China]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"[Sch. of Electr. Eng. & Comput. Sci., Peking Univ., Beijing, China]","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076122063","display_name":"Kalliopi Tsota","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Tsota","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, USA","Computer Science Department, University of California, Los Angeles, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050841063","display_name":"Bingjun Xiao","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bingjun Xiao","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, USA","Computer Science Department, University of California, Los Angeles, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"441","last_page":"446"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8248555064201355},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.743057131767273},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.7190812826156616},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.575461745262146},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5353456139564514},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4527277946472168},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.42364197969436646},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4070364534854889},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.3565066456794739},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34365397691726685},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.18222984671592712},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.17508170008659363},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11734598875045776}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8248555064201355},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.743057131767273},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.7190812826156616},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.575461745262146},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5353456139564514},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4527277946472168},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.42364197969436646},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4070364534854889},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.3565066456794739},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34365397691726685},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.18222984671592712},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.17508170008659363},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11734598875045776},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2013.6509636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2013.6509636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W1603813963","https://openalex.org/W1971840653","https://openalex.org/W1978226299","https://openalex.org/W1982924274","https://openalex.org/W1999116995","https://openalex.org/W2022271562","https://openalex.org/W2028762187","https://openalex.org/W2043643711","https://openalex.org/W2072175262","https://openalex.org/W2072542815","https://openalex.org/W2085456403","https://openalex.org/W2096117010","https://openalex.org/W2099184857","https://openalex.org/W2103848222","https://openalex.org/W2105616993","https://openalex.org/W2114871550","https://openalex.org/W2125831674","https://openalex.org/W2133286478","https://openalex.org/W2133367791","https://openalex.org/W2167841124","https://openalex.org/W2170957689","https://openalex.org/W2173471405","https://openalex.org/W2178873339","https://openalex.org/W2278564981","https://openalex.org/W3140720939","https://openalex.org/W3141126213","https://openalex.org/W3145272032","https://openalex.org/W3148798416","https://openalex.org/W3152105119","https://openalex.org/W4254477580","https://openalex.org/W6636335383","https://openalex.org/W6676061082","https://openalex.org/W6684847857"],"related_works":["https://openalex.org/W2169510384","https://openalex.org/W2077246255","https://openalex.org/W2967850598","https://openalex.org/W2304374807","https://openalex.org/W2045697850","https://openalex.org/W2012873180","https://openalex.org/W2156550631","https://openalex.org/W2155675690","https://openalex.org/W3197841175","https://openalex.org/W1563562883"],"abstract_inverted_index":{"One":[0],"of":[1,15,31,76,121,160],"the":[2,6,29,32,36,59,109,113,119,125,140,147,158,161,170],"necessary":[3],"requirements":[4],"for":[5,40],"placement":[7,131,148,164],"process":[8],"is":[9],"that":[10,144,154],"it":[11],"should":[12],"be":[13],"capable":[14],"generating":[16],"routable":[17],"solutions.":[18],"This":[19],"paper":[20],"describes":[21],"a":[22],"simple":[23],"but":[24],"effective":[25],"method":[26],"leading":[27],"to":[28,46,139],"reduction":[30,83],"routing":[33,48,171],"congestion":[34,49],"and":[35,50,99,111,134,167],"final":[37],"routed":[38],"wirelength":[39],"large-scale":[41],"mixed-size":[42],"designs.":[43],"In":[44],"order":[45],"reduce":[47],"improve":[51],"routability,":[52],"we":[53,135],"propose":[54,63],"blocking":[55],"narrow":[56,81],"regions":[57,67,94],"on":[58],"chip.":[60],"We":[61,117],"also":[62],"dummy-cell":[64,90],"insertion":[65,91],"inside":[66,92],"characterized":[68],"by":[69,84,103],"reduced":[70,96],"fixed-macro":[71,87,97],"density.":[72,116],"Our":[73],"placer":[74,123,156],"consists":[75],"three":[77],"major":[78],"components:":[79],"(i)":[80],"channel":[82],"performing":[85],"neighbor-based":[86],"inflation;":[88],"(ii)":[89],"large":[93],"with":[95],"density;":[98],"(iii)":[100],"pre-placement":[101],"inflation":[102],"detecting":[104],"tangled":[105],"logic":[106],"structures":[107],"in":[108,146],"netlist":[110],"minimizing":[112],"maximum":[114],"pin":[115],"evaluated":[118],"quality":[120],"our":[122,137,155],"using":[124],"newly":[126],"released":[127],"DAC":[128,162],"2012":[129,163],"routability-driven":[130],"contest":[132,165],"designs":[133,166],"compared":[136],"results":[138,152],"top":[141],"four":[142],"teams":[143],"participated":[145],"contest.":[149],"The":[150],"experimental":[151],"reveal":[153],"improves":[157],"routability":[159],"effectively":[168],"reduces":[169],"congestion.":[172]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":7}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
