{"id":"https://openalex.org/W2014636649","doi":"https://doi.org/10.1109/aspdac.2013.6509618","title":"Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs","display_name":"Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W2014636649","doi":"https://doi.org/10.1109/aspdac.2013.6509618","mag":"2014636649"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2013.6509618","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2013.6509618","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108201154","display_name":"Hsien-Kai Kuo","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hsien-Kai Kuo","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037101573","display_name":"Ta-Kan Yen","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ta-Kan Yen","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013913342","display_name":"Bo\u2010Cheng Lai","orcid":"https://orcid.org/0000-0002-9729-5196"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Bo-Cheng Charles Lai","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111925764","display_name":"Jing-Yang Jou","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jing-Yang Jou","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5108201154"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":2.5217,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.89197393,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8838818073272705},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7302169799804688},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7161164283752441},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.665285050868988},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.619773805141449},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.6143551468849182},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.6038161516189575},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.5666249394416809},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5369320511817932},{"id":"https://openalex.org/keywords/cache-oblivious-algorithm","display_name":"Cache-oblivious algorithm","score":0.41394442319869995},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3672102391719818},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.34279710054397583}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8838818073272705},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7302169799804688},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7161164283752441},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.665285050868988},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.619773805141449},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.6143551468849182},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6038161516189575},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.5666249394416809},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5369320511817932},{"id":"https://openalex.org/C59687516","wikidata":"https://www.wikidata.org/wiki/Q5015938","display_name":"Cache-oblivious algorithm","level":5,"score":0.41394442319869995},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3672102391719818},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.34279710054397583}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2013.6509618","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2013.6509618","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1968902482","https://openalex.org/W1976474269","https://openalex.org/W1979527452","https://openalex.org/W1981772986","https://openalex.org/W2058200712","https://openalex.org/W2074140323","https://openalex.org/W2088257029","https://openalex.org/W2100172689","https://openalex.org/W2117197583","https://openalex.org/W2128046183","https://openalex.org/W2128329055","https://openalex.org/W2150329270","https://openalex.org/W2155396321","https://openalex.org/W2161773701","https://openalex.org/W4231105337","https://openalex.org/W6644544826","https://openalex.org/W6682119398"],"related_works":["https://openalex.org/W2098406302","https://openalex.org/W2535115842","https://openalex.org/W2734782074","https://openalex.org/W2546991807","https://openalex.org/W2020176098","https://openalex.org/W2436169747","https://openalex.org/W2116323004","https://openalex.org/W2121191383","https://openalex.org/W2076114130","https://openalex.org/W1584415117"],"abstract_inverted_index":{"On-chip":[0],"shared":[1],"cache":[2,27,36,55,67,94,117,139,147],"is":[3],"effective":[4],"to":[5,34,89,105,114,164],"alleviate":[6],"the":[7,46,54,91,116,132,158],"memory":[8],"bottleneck":[9],"in":[10,50],"modern":[11],"many-core":[12],"systems,":[13],"such":[14],"as":[15,96,98],"GPGPUs.":[16,78],"However,":[17],"when":[18],"scheduling":[19,30,75,134],"numerous":[20],"concurrent":[21],"threads":[22,39],"on":[23,125],"a":[24,26,64,73,82,103],"GPGPU,":[25],"capacity":[28,68,95,118],"agnostic":[29],"scheme":[31,135],"could":[32],"lead":[33],"severe":[35],"contention":[37,56],"among":[38],"and":[40,141,150],"thus":[41],"significant":[42],"performance":[43],"degradation.":[44],"Moreover,":[45],"diverse":[47],"working":[48],"sets":[49],"irregular":[51],"applications":[52],"make":[53],"issue":[57,76],"an":[58,143],"even":[59],"more":[60,167],"serious":[61],"problem.":[62],"As":[63],"result,":[65],"taking":[66],"into":[69],"account":[70],"has":[71,110],"become":[72],"critical":[74],"of":[77,93,145],"This":[79],"paper":[80,109,155],"formulates":[81],"Cache":[83],"Capacity":[84],"Aware":[85],"Thread":[86],"Scheduling":[87],"Problem":[88],"capture":[90],"impact":[92],"well":[97],"different":[99],"architectural":[100],"considerations.":[101],"With":[102],"proof":[104],"be":[106,161],"NP-hard,":[107],"this":[108],"proposed":[111,133],"two":[112],"algorithms":[113],"perform":[115],"aware":[119],"thread":[120],"scheduling.":[121],"The":[122,154],"simulation":[123],"results":[124],"Nvidia's":[126],"Fermi":[127],"configuration":[128],"have":[129],"shown":[130],"that":[131],"can":[136,160],"effectively":[137],"avoid":[138],"contention,":[140],"achieve":[142],"average":[144],"44.7%":[146],"miss":[148],"reduction":[149],"28.5%":[151],"runtime":[152,159],"enhancement.":[153],"also":[156],"shows":[157],"enhanced":[162],"up":[163],"62.5%":[165],"for":[166],"complex":[168],"applications.":[169]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}