{"id":"https://openalex.org/W2051865944","doi":"https://doi.org/10.1109/aspdac.2012.6165059","title":"BTI-aware design using variable latency units","display_name":"BTI-aware design using variable latency units","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W2051865944","doi":"https://doi.org/10.1109/aspdac.2012.6165059","mag":"2051865944"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2012.6165059","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2012.6165059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043629600","display_name":"Saket Gupta","orcid":"https://orcid.org/0000-0003-4541-5798"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saket Gupta","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis,55455, USA,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis,55455, USA,","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068714995","display_name":"Sachin S. Sapatnekar","orcid":"https://orcid.org/0000-0002-5353-2364"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sachin S. Sapatnekar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis,55455, USA,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis,55455, USA,","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9993,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.78816119,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"775","last_page":"780"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6877463459968567},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6226961612701416},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5196679830551147},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.45604732632637024},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44791966676712036},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44225937128067017},{"id":"https://openalex.org/keywords/variable","display_name":"Variable (mathematics)","score":0.4275876581668854},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4275038540363312},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4193713665008545},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4157450497150421},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3675965666770935},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34266626834869385},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2239162027835846},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17705005407333374},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1238211989402771},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12210732698440552}],"concepts":[{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6877463459968567},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6226961612701416},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5196679830551147},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.45604732632637024},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44791966676712036},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44225937128067017},{"id":"https://openalex.org/C182365436","wikidata":"https://www.wikidata.org/wiki/Q50701","display_name":"Variable (mathematics)","level":2,"score":0.4275876581668854},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4275038540363312},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4193713665008545},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4157450497150421},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3675965666770935},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34266626834869385},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2239162027835846},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17705005407333374},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1238211989402771},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12210732698440552},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/aspdac.2012.6165059","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2012.6165059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.303.3908","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.303.3908","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.umn.edu/users/sachin/conf/aspdac12sg-vlu.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1991431227","https://openalex.org/W1991891926","https://openalex.org/W2110722301","https://openalex.org/W2134869654","https://openalex.org/W2136103183","https://openalex.org/W2150526221","https://openalex.org/W2150959181","https://openalex.org/W2154168135","https://openalex.org/W2155829479","https://openalex.org/W2160047208","https://openalex.org/W3143610959","https://openalex.org/W4236140030","https://openalex.org/W6648088779"],"related_works":["https://openalex.org/W1494292626","https://openalex.org/W3217430545","https://openalex.org/W2083793411","https://openalex.org/W1532891187","https://openalex.org/W2088006178","https://openalex.org/W2069145203","https://openalex.org/W2108605716","https://openalex.org/W63550369","https://openalex.org/W2098419840","https://openalex.org/W2766377030"],"abstract_inverted_index":{"Circuit":[0],"degradation":[1],"due":[2],"to":[3,10,74,81,91],"bias":[4,72],"temperature":[5],"instability":[6],"(BTI)":[7],"can":[8],"lead":[9],"timing":[11],"failures":[12],"in":[13,48,66,85],"digital":[14],"circuits.":[15],"We":[16],"develop":[17],"variable":[18],"latency":[19],"unit":[20],"(VLU)":[21],"based":[22],"BTI-aware":[23],"designs,":[24],"with":[25,68,104],"a":[26,105],"novel":[27],"scheme":[28,63],"for":[29,34],"multioutput":[30,60],"hold":[31,61],"logic":[32,62],"implementation":[33],"VLUs.":[35],"A":[36],"key":[37],"observation":[38],"is":[39,64],"the":[40,49,57,79],"identification":[41],"and":[42,54],"exploitation":[43],"of":[44,52,56,102,109],"specific":[45],"supersetting":[46],"patterns":[47],"two-dimensional":[50],"space":[51],"frequency":[53],"aging":[55],"circuit.":[58],"The":[59],"used":[65],"conjunction":[67],"an":[69,99],"adaptive":[70],"body":[71],"framework":[73],"achieve":[75],"high":[76],"performance,":[77],"allowing":[78],"design":[80,97],"be":[82],"easily":[83],"incorporated":[84],"traditional":[86],"synthesis":[87],"flows.":[88],"As":[89],"compared":[90],"conventional":[92],"combinational":[93],"BTI-resilience":[94],"scheme,":[95],"our":[96],"achieves":[98],"area":[100],"reduction":[101],"9.2%,":[103],"significant":[106],"throughput":[107],"enhancement":[108],"30.0%.":[110]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}