{"id":"https://openalex.org/W2142726962","doi":"https://doi.org/10.1109/aspdac.2012.6165045","title":"On error tolerance and Engineering Change with Partially Programmable Circuits","display_name":"On error tolerance and Engineering Change with Partially Programmable Circuits","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W2142726962","doi":"https://doi.org/10.1109/aspdac.2012.6165045","mag":"2142726962"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2012.6165045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2012.6165045","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016047575","display_name":"Hratch Mangassarian","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Hratch Mangassarian","raw_affiliation_strings":["ECE Department, University of Toronto, Toronto, ONT, Canada","ECE Dept., University of Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ECE Department, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"ECE Dept., University of Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073098982","display_name":"Hiroaki Yoshida","orcid":"https://orcid.org/0000-0002-5370-7451"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroaki Yoshida","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo, Japan","VLSI Design & Educ. Center, Univ. of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design & Educ. Center, Univ. of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009841786","display_name":"Andreas Veneris","orcid":"https://orcid.org/0000-0002-6309-8821"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andreas Veneris","raw_affiliation_strings":["ECE Department, University of Toronto, Toronto, ONT, Canada","ECE Dept., University of Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ECE Department, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"ECE Dept., University of Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068612356","display_name":"Shigeru Yamashita","orcid":"https://orcid.org/0000-0002-2279-4644"},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shigeru Yamashita","raw_affiliation_strings":["College of Information Science and Engineering, Ritsumeikan University, Japan","College of Information Sci. and Eng., Ritsumeikan Univ., Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Information Science and Engineering, Ritsumeikan University, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"College of Information Sci. and Eng., Ritsumeikan Univ., Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo, Japan","VLSI Design & Educ. Center, Univ. of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design & Educ. Center, Univ. of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":null,"first_page":"695","last_page":"700"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6986774802207947},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6646671891212463},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6157035827636719},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5492104291915894},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5482497811317444},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5342139005661011},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.481315016746521},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46670031547546387},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.466123104095459},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4557610750198364},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4434286057949066},{"id":"https://openalex.org/keywords/circuit-complexity","display_name":"Circuit complexity","score":0.4400619864463806},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.4114057421684265},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3995320498943329},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.39606088399887085},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3810789883136749},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3105704188346863},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17150548100471497},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.10439768433570862},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.10150328278541565},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0889115035533905}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6986774802207947},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6646671891212463},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6157035827636719},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5492104291915894},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5482497811317444},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5342139005661011},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.481315016746521},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46670031547546387},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.466123104095459},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4557610750198364},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4434286057949066},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.4400619864463806},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.4114057421684265},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3995320498943329},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.39606088399887085},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3810789883136749},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3105704188346863},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17150548100471497},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.10439768433570862},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.10150328278541565},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0889115035533905},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/aspdac.2012.6165045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2012.6165045","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.228.3365","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.228.3365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/%7Eveneris/12aspdac2.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1482661140","https://openalex.org/W1561638731","https://openalex.org/W1836852804","https://openalex.org/W2012999122","https://openalex.org/W2119841103","https://openalex.org/W2119913792","https://openalex.org/W2120185818","https://openalex.org/W2124882400","https://openalex.org/W2141389982","https://openalex.org/W2151335319","https://openalex.org/W2153125146","https://openalex.org/W2160121838","https://openalex.org/W2295683841","https://openalex.org/W2914069437","https://openalex.org/W3142089438","https://openalex.org/W4235244711","https://openalex.org/W4255143173","https://openalex.org/W6678403550","https://openalex.org/W6680874277","https://openalex.org/W6683638471","https://openalex.org/W6696851094","https://openalex.org/W7047819290"],"related_works":["https://openalex.org/W2808864279","https://openalex.org/W2125609625","https://openalex.org/W2155289750","https://openalex.org/W2159724425","https://openalex.org/W4231267350","https://openalex.org/W1565986912","https://openalex.org/W2117956479","https://openalex.org/W3105918491","https://openalex.org/W2053477566","https://openalex.org/W4379115868"],"abstract_inverted_index":{"The":[0,32,66],"growing":[1],"size,":[2],"density":[3],"and":[4,18,27,92,104,131,152],"complexity":[5],"of":[6,34,96,102,137,154],"modern":[7],"VLSI":[8],"chips":[9],"are":[10,85,126,143],"contributing":[11],"to":[12,87],"an":[13],"increase":[14],"in":[15,21,120],"hardware":[16],"faults":[17,103],"design":[19,30,93,105],"errors":[20,106],"the":[22,29,70,89,100,134,150,155],"silicon,":[23],"decreasing":[24],"manufacturing":[25],"yield":[26,44],"increasing":[28],"cycle.":[31],"use":[33],"Partially":[35],"Programmable":[36],"Circuits":[37],"(PPCs)":[38],"has":[39],"been":[40],"recently":[41],"proposed":[42,156],"for":[43,73,128,132],"enhancement":[45],"with":[46,63,76],"very":[47],"small":[48],"overhead.":[49],"This":[50],"new":[51],"circuit":[52],"structure":[53],"is":[54,122],"obtained":[55],"from":[56,147],"conventional":[57],"logic":[58],"by":[59],"replacing":[60],"some":[61],"subcircuits":[62],"programmable":[64],"LUTs.":[65],"present":[67],"paper":[68],"lays":[69],"theoretical":[71],"groundwork":[72],"evaluating":[74,145],"PPCs":[75,121,146],"Quantified":[77],"Boolean":[78],"Formula":[79],"(QBF)":[80],"satisfiability.":[81],"First,":[82],"QBF":[83,124],"models":[84],"constructed":[86],"calculate":[88],"fault":[90],"tolerance":[91,95],"error":[94],"a":[97,138],"PPC,":[98],"namely":[99],"percentages":[101],"that":[107],"can":[108],"be":[109],"masked":[110],"using":[111],"LUT":[112],"reconfigurations.":[113],"Next,":[114],"zero-cost":[115],"Engineering":[116],"Change":[117],"Order":[118],"(ECO)":[119],"investigated.":[123],"formulations":[125],"given":[127],"performing":[129],"ECOs,":[130],"quantifying":[133],"ECO":[135],"coverage":[136],"PPC":[139],"architecture.":[140],"Experimental":[141],"results":[142],"presented":[144],"[1],":[148],"demonstrating":[149],"applicability":[151],"accuracy":[153],"formulations.":[157]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
