{"id":"https://openalex.org/W1976154696","doi":"https://doi.org/10.1109/aspdac.2012.6164937","title":"LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits","display_name":"LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W1976154696","doi":"https://doi.org/10.1109/aspdac.2012.6164937","mag":"1976154696"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2012.6164937","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2012.6164937","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058812423","display_name":"Hailong Yao","orcid":"https://orcid.org/0000-0002-8750-3086"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Hailong Yao","raw_affiliation_strings":["EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China","EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100894724","display_name":"Yici Cai","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yici Cai","raw_affiliation_strings":["EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China","EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075905329","display_name":"Qiang Gao","orcid":"https://orcid.org/0000-0001-7860-6692"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Gao","raw_affiliation_strings":["EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China","EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5058812423"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":1.2275,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.80356199,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"157","last_page":"162"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.8149566650390625},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6730682849884033},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.6098770499229431},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.5813335180282593},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5636575818061829},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.5481420755386353},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5263059139251709},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5205241441726685},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.5026416778564453},{"id":"https://openalex.org/keywords/multipath-routing","display_name":"Multipath routing","score":0.48193979263305664},{"id":"https://openalex.org/keywords/equal-cost-multi-path-routing","display_name":"Equal-cost multi-path routing","score":0.4656819701194763},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.46334534883499146},{"id":"https://openalex.org/keywords/link-state-routing-protocol","display_name":"Link-state routing protocol","score":0.44074100255966187},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.4270375967025757},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.387977659702301},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.38605549931526184},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2885221242904663},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.2205602526664734},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.19406989216804504},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.17631134390830994},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16292735934257507},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16273951530456543},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15674525499343872}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.8149566650390625},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6730682849884033},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.6098770499229431},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.5813335180282593},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5636575818061829},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.5481420755386353},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5263059139251709},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5205241441726685},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.5026416778564453},{"id":"https://openalex.org/C76522221","wikidata":"https://www.wikidata.org/wiki/Q5035396","display_name":"Multipath routing","level":5,"score":0.48193979263305664},{"id":"https://openalex.org/C115443555","wikidata":"https://www.wikidata.org/wiki/Q5367790","display_name":"Equal-cost multi-path routing","level":5,"score":0.4656819701194763},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.46334534883499146},{"id":"https://openalex.org/C89305328","wikidata":"https://www.wikidata.org/wiki/Q1755411","display_name":"Link-state routing protocol","level":4,"score":0.44074100255966187},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.4270375967025757},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.387977659702301},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.38605549931526184},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2885221242904663},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.2205602526664734},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.19406989216804504},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.17631134390830994},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16292735934257507},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16273951530456543},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15674525499343872},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2012.6164937","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2012.6164937","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W2000200644","https://openalex.org/W2021501041","https://openalex.org/W2024182184","https://openalex.org/W2028326940","https://openalex.org/W2034118360","https://openalex.org/W2088956022","https://openalex.org/W2097066086","https://openalex.org/W2151933980","https://openalex.org/W2155444495","https://openalex.org/W2165465743","https://openalex.org/W2226297337","https://openalex.org/W2506224516","https://openalex.org/W2542166344","https://openalex.org/W3145069811","https://openalex.org/W4245484162","https://openalex.org/W4253167180","https://openalex.org/W6657784182","https://openalex.org/W6728929157"],"related_works":["https://openalex.org/W2156550631","https://openalex.org/W1563562883","https://openalex.org/W2185927297","https://openalex.org/W2376726667","https://openalex.org/W2155675690","https://openalex.org/W1571681534","https://openalex.org/W1980984060","https://openalex.org/W1964677779","https://openalex.org/W2111591643","https://openalex.org/W2391887037"],"abstract_inverted_index":{"Enabled":[0],"by":[1],"the":[2,9,46,60,71,75,84,89,101,106],"heterogeneous":[3],"integration":[4],"in":[5,19],"modern":[6],"System-On-Chips":[7],"(SOCs),":[8],"design":[10],"automation":[11],"for":[12,27,33,58,63,87,99],"analog":[13,29],"and":[14,92,96,113,120],"mixed":[15],"signal":[16],"circuit":[17],"components":[18],"SOCs":[20],"is":[21,117],"attracting":[22],"increasing":[23],"interests.":[24],"Matching":[25],"constraints":[26],"specific":[28],"signals":[30],"are":[31,111],"critical":[32],"correct":[34],"functionalities.":[35],"This":[36],"paper":[37],"presents":[38],"a":[39],"novel":[40],"single-layer":[41],"detailed":[42],"routing":[43,56,61,90,103],"algorithm":[44,81],"with":[45,83,105],"length":[47],"matching":[48,107],"constraint,":[49],"called":[50],"LEMAR.":[51],"LEMAR":[52,116],"features":[53],"an":[54,78,93],"innovative":[55],"model":[57],"partitioning":[59],"layout":[62],"wire":[64],"detouring,":[65],"effective":[66,119],"detouring":[67],"patterns":[68],"according":[69],"to":[70],"geometric":[72],"shapes":[73],"of":[74],"partitioned":[76],"tiles,":[77],"enhanced":[79],"A*-search":[80],"along":[82],"backtrack":[85],"technique":[86],"finding":[88,100],"path,":[91],"iterative":[94],"rip-up":[95],"reroute":[97],"procedure":[98],"feasible":[102],"solution":[104],"constraint.":[108],"Experimental":[109],"results":[110],"promising":[112],"show":[114],"that":[115],"both":[118],"efficient.":[121]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}