{"id":"https://openalex.org/W3151865651","doi":"https://doi.org/10.1109/aspdac.2011.5722312","title":"Design and chip implementation of a heterogeneous multi-core DSP","display_name":"Design and chip implementation of a heterogeneous multi-core DSP","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W3151865651","doi":"https://doi.org/10.1109/aspdac.2011.5722312","mag":"3151865651"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2011.5722312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041024729","display_name":"Shuming Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Shuming Chen","raw_affiliation_strings":["Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101792763","display_name":"Xiaowen Chen","orcid":"https://orcid.org/0000-0003-2558-8800"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaowen Chen","raw_affiliation_strings":["Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100955340","display_name":"Yi Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yi Xu","raw_affiliation_strings":["Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109218335","display_name":"Jianghua Wan","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianghua Wan","raw_affiliation_strings":["Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047072104","display_name":"Jianzhuang Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianzhuang Lu","raw_affiliation_strings":["Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056901189","display_name":"Xiangyuan Liu","orcid":"https://orcid.org/0009-0005-8513-0879"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiangyuan Liu","raw_affiliation_strings":["Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083377397","display_name":"Shenggang Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shenggang Chen","raw_affiliation_strings":["Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic and Microprocessor, School of Computer, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5041024729"],"corresponding_institution_ids":["https://openalex.org/I170215575"],"apc_list":null,"apc_paid":null,"fwci":0.5037,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.70525914,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"91","last_page":"92"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.7777337431907654},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6821017861366272},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6376810073852539},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5554563999176025},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5475706458091736},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.536057710647583},{"id":"https://openalex.org/keywords/texas-instruments-davinci","display_name":"Texas Instruments DaVinci","score":0.49156054854393005},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4808950424194336},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.44088977575302124},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.4116082787513733},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3703039288520813},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3239571452140808},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16313257813453674},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14941340684890747},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1265968382358551}],"concepts":[{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.7777337431907654},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6821017861366272},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6376810073852539},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5554563999176025},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5475706458091736},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.536057710647583},{"id":"https://openalex.org/C45549533","wikidata":"https://www.wikidata.org/wiki/Q7707766","display_name":"Texas Instruments DaVinci","level":4,"score":0.49156054854393005},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4808950424194336},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44088977575302124},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.4116082787513733},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3703039288520813},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3239571452140808},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16313257813453674},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14941340684890747},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1265968382358551}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2011.5722312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W130716219","https://openalex.org/W2096968694"],"related_works":["https://openalex.org/W2091059919","https://openalex.org/W134967625","https://openalex.org/W2084471986","https://openalex.org/W2208809382","https://openalex.org/W2362998035","https://openalex.org/W2336952395","https://openalex.org/W71470947","https://openalex.org/W2541382934","https://openalex.org/W2363708040","https://openalex.org/W2144552376"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3],"novel":[4],"heterogeneous":[5],"multi-core":[6],"Digital":[7],"Signal":[8],"Processor,":[9],"named":[10],"YHFT-QDSP,":[11],"hosting":[12],"one":[13],"RISC":[14],"CPU":[15,23,58],"core":[16,24,59],"and":[17,30,60,71,90],"four":[18,62],"VLIW":[19],"DSP":[20,34,63,75],"cores.":[21,76],"The":[22,43,77],"is":[25,52,79],"responsible":[26],"for":[27,53,68],"task":[28],"scheduling":[29],"management,":[31],"while":[32],"the":[33,57,61,65],"cores":[35],"take":[36],"charge":[37],"of":[38,48],"speeding":[39],"up":[40],"data":[41],"processing.":[42],"YHFT-QDSP":[44,78],"provides":[45],"three":[46],"kinds":[47],"interconnection":[49],"communication.":[50],"One":[51],"inner-chip":[54,70],"communication":[55,73],"between":[56],"cores,":[64],"other":[66],"two":[67],"both":[69],"inter-chip":[72],"amongst":[74],"implemented":[80],"under":[81],"SMIC":[82],"<sup":[83,97],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[84,98],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\u00ae</sup>":[85],"130nm":[86],"LVT":[87],"CMOS":[88],"technology":[89],"can":[91],"run":[92],"350MHz@1.2V":[93],"with":[94],"114.49":[95],"mm":[96],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[99],"die":[100],"area.":[101]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
