{"id":"https://openalex.org/W3151103669","doi":"https://doi.org/10.1109/aspdac.2011.5722311","title":"An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture","display_name":"An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W3151103669","doi":"https://doi.org/10.1109/aspdac.2011.5722311","mag":"3151103669"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2011.5722311","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057408827","display_name":"Komatsu Yoshiya","orcid":null},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yoshiya Komatsu","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102097711","display_name":"Shota Ishihara","orcid":null},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shota Ishihara","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070647966","display_name":"Masanori Hariyama","orcid":"https://orcid.org/0000-0002-1464-8807"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masanori Hariyama","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037191455","display_name":"Michitaka Kameyama","orcid":"https://orcid.org/0000-0002-4245-9907"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Michitaka Kameyama","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201537933"],"apc_list":null,"apc_paid":null,"fwci":0.4475,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.66182913,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"89","last_page":"90"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8344663381576538},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.7207991480827332},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.667748212814331},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.5257856845855713},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5028759837150574},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.47713375091552734},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46616584062576294},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.45812758803367615},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45441731810569763},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4176996350288391},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36751943826675415},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24458041787147522},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.24345499277114868},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07085356116294861},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0668904185295105}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8344663381576538},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.7207991480827332},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.667748212814331},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.5257856845855713},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5028759837150574},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.47713375091552734},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46616584062576294},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.45812758803367615},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45441731810569763},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4176996350288391},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36751943826675415},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24458041787147522},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.24345499277114868},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07085356116294861},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0668904185295105},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2011.5722311","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2128723913","https://openalex.org/W2487142227"],"related_works":["https://openalex.org/W2116677773","https://openalex.org/W3014521742","https://openalex.org/W2155261584","https://openalex.org/W2111241003","https://openalex.org/W2584231425","https://openalex.org/W2150611273","https://openalex.org/W4207086172","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W4301373716"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"asynchronous":[4],"FPGA":[5,44],"that":[6],"combines":[7],"four-phase":[8],"dual-rail":[9,17],"encoding":[10,18,32],"and":[11,24,36,53],"LEDR":[12,31],"(Level-Encoded":[13],"Dual-Rail)":[14],"encoding.":[15],"Four-phase":[16],"is":[19,45,66],"used":[20],"for":[21,33,70],"small":[22],"area":[23],"low":[25,37],"power":[26,38,64],"of":[27,39,73],"function":[28],"units,":[29],"while":[30],"high":[34],"throughput":[35],"data":[40],"transfer.":[41],"The":[42],"proposed":[43],"fabricated":[46],"in":[47],"the":[48,60,63,71],"e-Shuttle":[49],"65nm":[50],"CMOS":[51],"process":[52],"operates":[54],"at":[55],"870":[56],"MHz.":[57],"Compared":[58],"to":[59],"synchronous":[61],"FPGA,":[62],"consumption":[65],"reduced":[67],"by":[68],"38%":[69],"workload":[72],"15%.":[74]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}