{"id":"https://openalex.org/W3143548627","doi":"https://doi.org/10.1109/aspdac.2011.5722309","title":"Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism","display_name":"Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W3143548627","doi":"https://doi.org/10.1109/aspdac.2011.5722309","mag":"3143548627"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2011.5722309","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722309","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063573667","display_name":"Yu-Tzu Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I4880106","display_name":"Feng Chia University","ror":"https://ror.org/05vhczg54","country_code":"TW","type":"education","lineage":["https://openalex.org/I4880106"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Tzu Tsai","raw_affiliation_strings":["Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan","institution_ids":["https://openalex.org/I4880106"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110259318","display_name":"Cheng-Chih Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I4880106","display_name":"Feng Chia University","ror":"https://ror.org/05vhczg54","country_code":"TW","type":"education","lineage":["https://openalex.org/I4880106"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-Chih Tsai","raw_affiliation_strings":["Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan","institution_ids":["https://openalex.org/I4880106"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111962498","display_name":"Cheng-An Chien","orcid":null},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]},{"id":"https://openalex.org/I4880106","display_name":"Feng Chia University","ror":"https://ror.org/05vhczg54","country_code":"TW","type":"education","lineage":["https://openalex.org/I4880106"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-An Chien","raw_affiliation_strings":["Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan","institution_ids":["https://openalex.org/I4880106"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041509052","display_name":"Ching-Hwa Cheng","orcid":"https://orcid.org/0000-0003-0587-237X"},"institutions":[{"id":"https://openalex.org/I4880106","display_name":"Feng Chia University","ror":"https://ror.org/05vhczg54","country_code":"TW","type":"education","lineage":["https://openalex.org/I4880106"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Hwa Cheng","raw_affiliation_strings":["Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan","institution_ids":["https://openalex.org/I4880106"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022312926","display_name":"Jiun-In Guo","orcid":"https://orcid.org/0000-0003-0402-2621"},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]},{"id":"https://openalex.org/I4880106","display_name":"Feng Chia University","ror":"https://ror.org/05vhczg54","country_code":"TW","type":"education","lineage":["https://openalex.org/I4880106"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jiun-In Guo","raw_affiliation_strings":["Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Department of Electronic Engineering, Feng Chia University FCU, Taichung, Taiwan","institution_ids":["https://openalex.org/I4880106"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2703,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.67853365,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"85","last_page":"86"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6705536842346191},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.6329349279403687},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.618768036365509},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6092263460159302},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.6016666889190674},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6015153527259827},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5011293888092041},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.4991943836212158},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49647098779678345},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.48812898993492126},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.48563352227211},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.477166086435318},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.46500858664512634},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.46466031670570374},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4638206362724304},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4307183027267456},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.38139912486076355},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36500298976898193},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.34521329402923584},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25088804960250854},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.20398783683776855}],"concepts":[{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6705536842346191},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.6329349279403687},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.618768036365509},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6092263460159302},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.6016666889190674},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6015153527259827},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5011293888092041},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.4991943836212158},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49647098779678345},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.48812898993492126},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.48563352227211},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.477166086435318},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.46500858664512634},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.46466031670570374},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4638206362724304},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4307183027267456},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.38139912486076355},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36500298976898193},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.34521329402923584},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25088804960250854},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.20398783683776855},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2011.5722309","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722309","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6800000071525574,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2108971405"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2051886008","https://openalex.org/W2535520145","https://openalex.org/W1716153929","https://openalex.org/W2743305891","https://openalex.org/W3011978806","https://openalex.org/W2059530328","https://openalex.org/W3205162826","https://openalex.org/W2610167993"],"abstract_inverted_index":{"The":[0,26,39,62],"high":[1,36],"speed":[2],"dual":[3],"phase":[4],"operation":[5],"domino":[6],"circuit,":[7],"which":[8],"includes":[9],"high-performance":[10],"and":[11,16],"reliable":[12],"characteristics":[13],"is":[14,24,55],"proposed,":[15],"the":[17,32,71],"circuit":[18],"design":[19,34],"technique":[20],"with":[21,49],"practical":[22],"implementation":[23],"presented.":[25],"cell-based":[27],"automatic":[28],"synthesis":[29],"flow":[30],"supports":[31],"quick":[33],"of":[35,42],"performance":[37,52,67],"chips.":[38],"test":[40,63],"chip":[41,64],"a":[43,50],"dual-phase":[44],"64":[45],"bit":[46],"high-speed":[47],"multiplier":[48],"built-in":[51],"adjustment":[53],"mechanism":[54],"successfully":[56],"validated":[57],"using":[58],"TSMC":[59],"0.18":[60],"technology.":[61],"shows":[65],"\u00d72.7":[66],"improvement":[68],"compared":[69],"to":[70],"conventional":[72],"static":[73],"CMOS":[74],"logic":[75],"design.":[76]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}