{"id":"https://openalex.org/W3140703759","doi":"https://doi.org/10.1109/aspdac.2011.5722288","title":"A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS","display_name":"A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W3140703759","doi":"https://doi.org/10.1109/aspdac.2011.5722288","mag":"3140703759"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2011.5722288","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085875405","display_name":"Benjamin Devlin","orcid":"https://orcid.org/0009-0008-2823-549X"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Benjamin Devlin","raw_affiliation_strings":["Department of Electronic Engineering, University of Tokyo, Bunkyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["VLSI Design and Education Center, VDEC, University of Tokyo, Bunkyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, VDEC, University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["VLSI Design and Education Center, VDEC, University of Tokyo, Bunkyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, VDEC, University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5085875405"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.39141481,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"75","last_page":"76"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7660622596740723},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.6994019746780396},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6767926216125488},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6314409375190735},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.616323709487915},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5653392672538757},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5264878273010254},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47262808680534363},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.46619123220443726},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46279215812683105},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34910398721694946},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3340767025947571},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23199430108070374},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.08257541060447693}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7660622596740723},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.6994019746780396},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6767926216125488},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6314409375190735},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.616323709487915},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5653392672538757},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5264878273010254},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47262808680534363},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.46619123220443726},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46279215812683105},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34910398721694946},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3340767025947571},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23199430108070374},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.08257541060447693},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2011.5722288","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7400000095367432,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321679","display_name":"Ministry of Economy, Trade and Industry","ror":"https://ror.org/055tm7f07"},{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320334833","display_name":"Agency for Natural Resources and Energy","ror":"https://ror.org/055tm7f07"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2029736024","https://openalex.org/W2123222669","https://openalex.org/W2123392516"],"related_works":["https://openalex.org/W2117300767","https://openalex.org/W2131696304","https://openalex.org/W2374017528","https://openalex.org/W2295734895","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W2366554144","https://openalex.org/W2024574431","https://openalex.org/W2003435315","https://openalex.org/W2014521732"],"abstract_inverted_index":{"We":[0,76],"have":[1],"designed":[2],"and":[3,11,85],"measured":[4,67,77],"the":[5,45,78,88],"performance":[6],"against":[7],"power":[8],"supply":[9],"bounce":[10],"aging":[12,81],"of":[13,35,47],"a":[14,32,48,57,72,100],"Self":[15,38],"Synchronous":[16,39,101],"FPGA":[17],"(SSFPGA)":[18],"in":[19],"65nm":[20],"CMOS":[21],"which":[22],"achieves":[23],"2.97GHz":[24],"throughput":[25,59],"at":[26,68],"1.2V.":[27],"The":[28],"proposed":[29],"SSFPGA":[30,79,89],"employs":[31],"38\u00d738":[33],"array":[34],"4-input,":[36],"3-stage":[37],"Configurable":[40],"Logic":[41],"Blocks":[42],"(SSCLB),":[43],"with":[44,82],"introduction":[46],"new":[49],"dual":[50],"tree-divider":[51],"4":[52],"input":[53],"LUT":[54],"to":[55,99],"achieve":[56],"4.5\u00d7":[58],"improvement":[60],"over":[61],"our":[62],"previous":[63],"model.":[64],"Energy":[65],"was":[66],"3.23":[69],"pJ/block/cycle":[70],"using":[71],"custom":[73],"built":[74],"board.":[75],"for":[80],"accelerated":[83],"degradation":[84],"results":[86],"show":[87],"has":[90],"8%":[91],"longer":[92],"time":[93],"margin":[94],"before":[95],"chip":[96],"malfunctions":[97],"compared":[98],"FPGA.":[102]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
