{"id":"https://openalex.org/W3143592324","doi":"https://doi.org/10.1109/aspdac.2011.5722282","title":"AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors","display_name":"AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W3143592324","doi":"https://doi.org/10.1109/aspdac.2011.5722282","mag":"3143592324"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2011.5722282","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722282","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076543905","display_name":"Abhishek Sinkar","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Abhishek Sinkar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037648751","display_name":"Nam Sung Kim","orcid":"https://orcid.org/0000-0002-0442-5634"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nam Sung Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5076543905"],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":0.265,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.67190745,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":null,"first_page":"725","last_page":"730"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8719522953033447},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5974305868148804},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5736023783683777},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5624862909317017},{"id":"https://openalex.org/keywords/maximum-power-principle","display_name":"Maximum power principle","score":0.5422632694244385},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.48195168375968933},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.48158717155456543},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.44436272978782654},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.44210341572761536},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.42619869112968445},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.42510849237442017},{"id":"https://openalex.org/keywords/electrical-efficiency","display_name":"Electrical efficiency","score":0.4237963557243347},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3629736304283142},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2696051597595215},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.15817534923553467},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.0881814956665039},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.07816675305366516}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8719522953033447},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5974305868148804},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5736023783683777},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5624862909317017},{"id":"https://openalex.org/C116615679","wikidata":"https://www.wikidata.org/wiki/Q6795908","display_name":"Maximum power principle","level":3,"score":0.5422632694244385},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.48195168375968933},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.48158717155456543},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.44436272978782654},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.44210341572761536},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.42619869112968445},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.42510849237442017},{"id":"https://openalex.org/C118993495","wikidata":"https://www.wikidata.org/wiki/Q5042828","display_name":"Electrical efficiency","level":3,"score":0.4237963557243347},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3629736304283142},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2696051597595215},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.15817534923553467},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0881814956665039},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.07816675305366516},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2011.5722282","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722282","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1979527452","https://openalex.org/W2078423579","https://openalex.org/W2107766185","https://openalex.org/W2116359224","https://openalex.org/W2127039903","https://openalex.org/W2150283124","https://openalex.org/W2154169726","https://openalex.org/W2170509664","https://openalex.org/W6684756257"],"related_works":["https://openalex.org/W1680268817","https://openalex.org/W2154169726","https://openalex.org/W2475077126","https://openalex.org/W2972962268","https://openalex.org/W3185548375","https://openalex.org/W2137755186","https://openalex.org/W2141721356","https://openalex.org/W576646735","https://openalex.org/W2143954265","https://openalex.org/W2116656154"],"abstract_inverted_index":{"Power-gating":[0],"devices":[1,27,109,172,191],"incur":[2],"a":[3,57,100,152],"small":[4],"amount":[5],"of":[6,22,53,60,78,89,94,107,113,131,170,189,211],"voltage":[7,45,115,206],"drop":[8,34],"across":[9],"them":[10],"when":[11],"they":[12],"are":[13,28],"on":[14,82],"in":[15,91],"active":[16],"mode,":[17],"degrading":[18],"the":[19,33,36,76,92,105,111,122,158,168,186,196,203,209],"maximum":[20,61,84],"frequency":[21,37,62,85,179],"processors.":[23,133,184],"Thus,":[24],"large":[25,58],"power-gating":[26,79,108,171,190],"often":[29],"implemented":[30],"to":[31,50,67],"minimize":[32,121],"(thus":[35],"degradation),":[38],"requiring":[39],"considerable":[40],"die":[41,214],"area.":[42],"Meanwhile,":[43],"adaptive":[44,114],"scaling":[46,116],"has":[47],"been":[48],"used":[49],"improve":[51],"yield":[52],"power-constrained":[54,132,182],"processors":[55,90,143,194],"exhibiting":[56],"spread":[59],"and":[63,86,110,128,139,164],"total":[64,87],"power":[65,88,129],"due":[66],"process":[68,95],"variations.":[69],"In":[70],"this":[71],"paper,":[72],"first,":[73],"we":[74,98,120,135],"analyze":[75],"impact":[77],"device":[80,123],"size":[81,106,124,169,188],"both":[83,104,162],"presence":[93],"variation.":[96],"Second,":[97],"propose":[99],"methodology":[101],"that":[102,119,157],"optimizes":[103],"degree":[112],"jointly":[117],"such":[118],"while":[125,202],"maximizing":[126],"performance":[127],"efficiency":[130],"Finally,":[134],"extend":[136],"our":[137],"analysis":[138],"optimization":[140,160],"for":[141,181,192],"multi-core":[142,183,193],"adopting":[144],"frequency-island":[145,197],"clocking":[146,198],"scheme.":[147],"Our":[148],"experimental":[149],"results":[150],"using":[151,195],"32nm":[153],"technology":[154],"model":[155],"demonstrates":[156],"joint":[159],"considering":[161],"die-to-die":[163],"within-die":[165],"variations":[166],"reduces":[167],"by":[173],"more":[174],"than":[175],"50%":[176],"with":[177],"3%":[178],"improvement":[180],"Further,":[185],"optimal":[187,204],"scheme":[199],"increases":[200],"gradually":[201],"supply":[205],"decreases":[207],"as":[208],"number":[210],"cores":[212],"per":[213],"increases.":[215]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
