{"id":"https://openalex.org/W3140929758","doi":"https://doi.org/10.1109/aspdac.2011.5722237","title":"Managing complexity in design debugging with sequential abstraction and refinement","display_name":"Managing complexity in design debugging with sequential abstraction and refinement","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W3140929758","doi":"https://doi.org/10.1109/aspdac.2011.5722237","mag":"3140929758"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2011.5722237","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722237","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070019319","display_name":"Brian Keng","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Brian Keng","raw_affiliation_strings":["ECE Department, University of Toronto, Toronto, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"ECE Department, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009841786","display_name":"Andreas Veneris","orcid":"https://orcid.org/0000-0002-6309-8821"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andreas Veneris","raw_affiliation_strings":["CS Department, University of Toronto, Toronto, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"CS Department, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5070019319"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":1.0075,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.79822468,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"4","issue":null,"first_page":"479","last_page":"484"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.9237445592880249},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8587899208068848},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.7378354072570801},{"id":"https://openalex.org/keywords/algorithmic-program-debugging","display_name":"Algorithmic program debugging","score":0.5429023504257202},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.538074791431427},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4545948803424835},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.42721328139305115},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.41342487931251526},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4088844656944275},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3603641986846924},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35413092374801636},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3495446443557739},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20567253232002258}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.9237445592880249},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8587899208068848},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.7378354072570801},{"id":"https://openalex.org/C136388014","wikidata":"https://www.wikidata.org/wiki/Q17084976","display_name":"Algorithmic program debugging","level":3,"score":0.5429023504257202},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.538074791431427},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4545948803424835},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.42721328139305115},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.41342487931251526},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4088844656944275},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3603641986846924},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35413092374801636},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3495446443557739},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20567253232002258},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2011.5722237","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722237","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1513012091","https://openalex.org/W1519854356","https://openalex.org/W1602612484","https://openalex.org/W1836483134","https://openalex.org/W1979903718","https://openalex.org/W2096541971","https://openalex.org/W2103351789","https://openalex.org/W2123298155","https://openalex.org/W2141808364","https://openalex.org/W2144606498","https://openalex.org/W2151387544","https://openalex.org/W2157373763","https://openalex.org/W2157686813","https://openalex.org/W3150068362","https://openalex.org/W6675375035","https://openalex.org/W6814269298"],"related_works":["https://openalex.org/W2396596882","https://openalex.org/W2119199043","https://openalex.org/W2801084903","https://openalex.org/W2377280071","https://openalex.org/W2060682672","https://openalex.org/W2375626968","https://openalex.org/W2098290990","https://openalex.org/W4242908235","https://openalex.org/W1520271518","https://openalex.org/W2294325978"],"abstract_inverted_index":{"Design":[0],"debugging":[1,35,45,62,148],"is":[2,36,85,105,124],"becoming":[3],"an":[4],"increasingly":[5],"difficult":[6],"task":[7],"in":[8,113,145],"the":[9,14,44,47,51,61,68,78,87,91,121,137,140],"VLSI":[10],"design":[11,34,48,70],"flow":[12],"with":[13,74],"growing":[15],"size":[16,49],"of":[17,43,67,77,110,142],"modern":[18],"designs":[19],"and":[20,30,50,71],"their":[21],"error":[22,52],"traces.":[23],"In":[24],"this":[25,143],"work,":[26],"a":[27],"novel":[28],"abstraction":[29,56],"refinement":[31,88,103,109],"technique":[32,57,138],"for":[33,129],"presented":[37],"that":[38,120],"addresses":[39],"two":[40],"key":[41],"components":[42],"complexity,":[46],"trace":[53],"length.":[54],"The":[55],"works":[58],"by":[59,64,107],"under-approximating":[60],"problem":[63,84],"removing":[65],"modules":[66,98],"original":[69],"replacing":[72],"them":[73],"simulated":[75],"values":[76],"erroneous":[79],"circuit.":[80],"After":[81],"each":[82],"abstract":[83],"solved,":[86],"strategy":[89,104],"uses":[90],"resulting":[92],"UNSAT":[93],"core":[94],"to":[95,115,126,133],"direct":[96],"which":[97],"should":[99],"be":[100],"refined.":[101],"This":[102],"extended":[106],"allowing":[108],"across":[111],"time-frames":[112],"addition":[114],"modules.":[116],"Experimental":[117],"results":[118],"show":[119],"proposed":[122],"algorithm":[123],"able":[125],"return":[127],"solutions":[128],"all":[130],"instances":[131],"compared":[132],"only":[134],"41%":[135],"without":[136],"demonstrating":[139],"viability":[141],"approach":[144],"tackling":[146],"real-world":[147],"problems.":[149]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}