{"id":"https://openalex.org/W3145573110","doi":"https://doi.org/10.1109/aspdac.2011.5722235","title":"Parallel cross-layer optimization of high-level synthesis and physical design","display_name":"Parallel cross-layer optimization of high-level synthesis and physical design","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W3145573110","doi":"https://doi.org/10.1109/aspdac.2011.5722235","mag":"3145573110"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2011.5722235","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722235","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074143608","display_name":"James R. Williamson","orcid":"https://orcid.org/0000-0002-8772-468X"},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"James Williamson","raw_affiliation_strings":["ECEE, University of Colorado, Boulder, USA"],"affiliations":[{"raw_affiliation_string":"ECEE, University of Colorado, Boulder, USA","institution_ids":["https://openalex.org/I188538660"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081521266","display_name":"Yinghai Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yinghai Lu","raw_affiliation_strings":["EECS, Northwestern University, USA"],"affiliations":[{"raw_affiliation_string":"EECS, Northwestern University, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004722925","display_name":"Li Shang","orcid":"https://orcid.org/0000-0003-3944-7531"},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Li Shang","raw_affiliation_strings":["ECEE, University of Colorado, Boulder, USA"],"affiliations":[{"raw_affiliation_string":"ECEE, University of Colorado, Boulder, USA","institution_ids":["https://openalex.org/I188538660"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103038285","display_name":"Hai Zhou","orcid":"https://orcid.org/0000-0003-4824-7179"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["CN","US"],"is_corresponding":false,"raw_author_name":"Hai Zhou","raw_affiliation_strings":["EECS, Northwestern University, USA","State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"EECS, Northwestern University, USA","institution_ids":["https://openalex.org/I111979921"]},{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064213921","display_name":"Xuan Zeng","orcid":"https://orcid.org/0000-0002-8097-4053"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuan Zeng","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5074143608"],"corresponding_institution_ids":["https://openalex.org/I188538660"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.39426451,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"467","last_page":"472"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7412946820259094},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.6709519624710083},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6485046148300171},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6354873180389404},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6239386796951294},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5957647562026978},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5484423041343689},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5151190161705017},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.5120344758033752},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5036608576774597},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.46652066707611084},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.4524208605289459},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4521782398223877},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.355043888092041},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3393325209617615},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2755752205848694},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2588841915130615},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21181318163871765}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7412946820259094},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.6709519624710083},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6485046148300171},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6354873180389404},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6239386796951294},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5957647562026978},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5484423041343689},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5151190161705017},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.5120344758033752},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5036608576774597},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.46652066707611084},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.4524208605289459},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4521782398223877},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.355043888092041},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3393325209617615},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2755752205848694},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2588841915130615},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21181318163871765},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2011.5722235","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2011.5722235","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1996746141","https://openalex.org/W2023462222","https://openalex.org/W2074140323","https://openalex.org/W2105441386","https://openalex.org/W2121318787","https://openalex.org/W2123424649","https://openalex.org/W2130290229","https://openalex.org/W2131979475","https://openalex.org/W2133250872","https://openalex.org/W2159715864","https://openalex.org/W2163190884","https://openalex.org/W2163961680","https://openalex.org/W2557929373","https://openalex.org/W3144573862","https://openalex.org/W3146952922","https://openalex.org/W4256007160","https://openalex.org/W6674301526","https://openalex.org/W6679953985"],"related_works":["https://openalex.org/W2246407281","https://openalex.org/W2735446578","https://openalex.org/W2743305891","https://openalex.org/W1975701649","https://openalex.org/W3205162826","https://openalex.org/W4321510758","https://openalex.org/W2110346573","https://openalex.org/W2154454108","https://openalex.org/W2610167993","https://openalex.org/W2056740847"],"abstract_inverted_index":{"Integrated":[0],"circuit":[1],"(IC)":[2],"design":[3,13,19,27,41,44,47,65,81,95,118,128,134,155],"automation":[4],"has":[5],"traditionally":[6],"followed":[7],"a":[8,50,87,140],"hierarchical":[9],"approach.":[10],"Modern":[11],"IC":[12,133],"flow":[14,66],"is":[15,49],"divided":[16],"into":[17],"sequentially-addressed":[18],"and":[20,29,57,90,106,125,146],"optimization":[21],"layers;":[22],"each":[23],"successively":[24],"finer":[25],"in":[26,34,63,76,104],"detail":[28],"data":[30],"granularity":[31],"while":[32],"increasing":[33],"computational":[35,102],"complexity.":[36],"Eventual":[37],"agreement":[38],"across":[39],"the":[40,78,94,99,113,123,151],"layers":[42,60,82,129],"signals":[43],"closure.":[45],"Obtaining":[46],"closure":[48],"continual":[51],"problem,":[52],"as":[53,150],"lack":[54],"of":[55,93,116,163],"awareness":[56],"interaction":[58],"between":[59,80],"often":[61],"results":[62,158],"multiple":[64,117],"iterations.":[67],"In":[68,136],"this":[69],"work,":[70],"we":[71,121,138],"propose":[72],"parallel":[73,101,131],"cross-layer":[74,132],"optimization,":[75],"which":[77],"boundaries":[79],"are":[83],"broken,":[84],"allowing":[85],"for":[86,130],"more":[88],"informed":[89],"efficient":[91],"exploration":[92],"space.":[96],"We":[97],"leverage":[98],"heterogeneous":[100,114],"power":[103],"current":[105],"upcoming":[107],"multi-core/many-core":[108],"computation":[109],"platforms":[110],"to":[111],"suite":[112],"characteristics":[115],"layers.":[119],"Specifically,":[120],"unify":[122],"highlevel":[124],"physical":[126,153],"synthesis":[127,154],"optimization.":[135],"addition,":[137],"introduce":[139],"massively-parallel":[141],"GPU":[142],"floorplanner":[143],"with":[144],"local":[145],"global":[147],"convergence":[148],"test":[149],"proposed":[152],"layer.":[156],"Our":[157],"show":[159],"average":[160],"performance":[161],"gains":[162],"11X":[164],"speed-up":[165],"over":[166],"state-of-the-art.":[167]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
