{"id":"https://openalex.org/W3144573862","doi":"https://doi.org/10.1109/aspdac.2010.5419903","title":"SCGPSim: A fast SystemC simulator on GPUs","display_name":"SCGPSim: A fast SystemC simulator on GPUs","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W3144573862","doi":"https://doi.org/10.1109/aspdac.2010.5419903","mag":"3144573862"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2010.5419903","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419903","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008338155","display_name":"Mahesh Nanjundappa","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M. Nanjundappa","raw_affiliation_strings":["FERMAT Lab, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"FERMAT Lab, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074065388","display_name":"Hiren Patel","orcid":"https://orcid.org/0000-0003-2750-4471"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"H.D. Patel","raw_affiliation_strings":["Department of ECE, University of Waterloo, Waterloo, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Department of ECE, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043317855","display_name":"Bijoy A. Jose","orcid":"https://orcid.org/0000-0002-9541-4286"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B.A. Jose","raw_affiliation_strings":["FERMAT Lab, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"FERMAT Lab, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021517996","display_name":"Sandeep K. Shukla","orcid":"https://orcid.org/0000-0001-5525-7426"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.K. Shukla","raw_affiliation_strings":["FERMAT Lab, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"FERMAT Lab, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5008338155"],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":4.7441,"has_fulltext":false,"cited_by_count":38,"citation_normalized_percentile":{"value":0.95547846,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9251925945281982},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8844791650772095},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.709792971611023},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.5925341844558716},{"id":"https://openalex.org/keywords/discrete-event-simulation","display_name":"Discrete event simulation","score":0.5575928688049316},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.49263983964920044},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.4890361726284027},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4654890298843384},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.445911705493927},{"id":"https://openalex.org/keywords/model-of-computation","display_name":"Model of computation","score":0.4323594570159912},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.39273613691329956},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37787288427352905},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.23388418555259705},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.1448100209236145},{"id":"https://openalex.org/keywords/computer-graphics","display_name":"Computer graphics (images)","score":0.1413297951221466}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9251925945281982},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8844791650772095},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.709792971611023},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.5925341844558716},{"id":"https://openalex.org/C147203929","wikidata":"https://www.wikidata.org/wiki/Q574814","display_name":"Discrete event simulation","level":2,"score":0.5575928688049316},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.49263983964920044},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.4890361726284027},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4654890298843384},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.445911705493927},{"id":"https://openalex.org/C184596265","wikidata":"https://www.wikidata.org/wiki/Q2651576","display_name":"Model of computation","level":3,"score":0.4323594570159912},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.39273613691329956},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37787288427352905},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.23388418555259705},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.1448100209236145},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.1413297951221466}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2010.5419903","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419903","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7200000286102295}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W44583000","https://openalex.org/W2074100014","https://openalex.org/W2098950324","https://openalex.org/W2139962185","https://openalex.org/W3140181672","https://openalex.org/W4252583823","https://openalex.org/W6981018740"],"related_works":["https://openalex.org/W4256575154","https://openalex.org/W1963774445","https://openalex.org/W2063411778","https://openalex.org/W2096955763","https://openalex.org/W2135428045","https://openalex.org/W2016176910","https://openalex.org/W2079291856","https://openalex.org/W3148142469","https://openalex.org/W2125436261","https://openalex.org/W2168814075"],"abstract_inverted_index":{"The":[0,122,137],"main":[1],"objective":[2],"of":[3,13,26,49,51,56,81,89,128,147],"this":[4],"paper":[5],"is":[6,79,99],"to":[7,109,172],"speed":[8],"up":[9],"the":[10,17,23,47,66,72,86,125,129,143,189],"simulation":[11,41,97,126,150,167,190],"performance":[12,191],"SystemC":[14,73,112],"designs":[15,131],"at":[16],"RTL":[18],"abstraction":[19],"level":[20],"by":[21,29,45,132],"exploiting":[22],"high":[24],"degree":[25],"parallelism":[27],"afforded":[28],"today's":[30],"general":[31],"purpose":[32],"graphics":[33],"processors":[34],"(GPGPUs).":[35],"Our":[36,96],"approach":[37],"parallelizes":[38],"SystemC's":[39],"discrete-event":[40],"(DES)":[42],"on":[43,85,94],"GPGPUs":[44],"transforming":[46],"model":[48,55,69,78],"computation":[50],"DES":[52],"into":[53,114],"a":[54,105],"concurrent":[57],"threads":[58],"that":[59,175,184],"synchronize":[60],"as":[61,160],"and":[62,102,163],"when":[63],"necessary.":[64],"Unlike":[65],"cooperative":[67],"threading":[68,77],"employed":[70],"in":[71,83],"reference":[74],"implementation,":[75],"our":[76,176],"capable":[80],"executing":[82],"parallel":[84,145],"large":[87],"number":[88],"simple":[90],"processing":[91],"units":[92],"available":[93],"GPUs.":[95],"infrastructure":[98],"called":[100],"SCGPSim":[101],"it":[103],"includes":[104],"source-to-source":[106],"(S2S)":[107],"translator":[108,123],"transform":[110],"synthesizable":[111],"models":[113,140],"parallelly":[115],"executable":[116],"programs":[117],"targeting":[118],"an":[119],"NVIDIA":[120],"GPU.":[121],"retains":[124],"semantics":[127,134],"original":[130],"applying":[133],"preserving":[135],"transformations.":[136],"resulting":[138],"transformed":[139],"mapped":[141],"onto":[142],"massively":[144],"architecture":[146],"GPUs":[148],"improve":[149,188],"efficiency":[151],"quite":[152],"substantially.":[153],"Preliminary":[154],"experiments":[155],"with":[156],"varying-sized":[157],"examples":[158],"such":[159],"AES,":[161],"ALU,":[162],"FIR":[164],"have":[165],"shown":[166],"speed-ups":[168],"ranging":[169],"from":[170],"30\u00d7":[171],"100\u00d7.":[173],"Considering":[174],"transformations":[177],"are":[178],"not":[179],"yet":[180],"optimized,":[181],"we":[182],"believe":[183],"optimizing":[185],"them":[186],"will":[187],"even":[192],"further.":[193]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}