{"id":"https://openalex.org/W4248399305","doi":"https://doi.org/10.1109/aspdac.2010.5419850","title":"Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization","display_name":"Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W4248399305","doi":"https://doi.org/10.1109/aspdac.2010.5419850"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2010.5419850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061699611","display_name":"Xin-Wei Shih","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Xin-Wei Shih","raw_affiliation_strings":["Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009882050","display_name":"Chung-Chun Cheng","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Chun Cheng","raw_affiliation_strings":["Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006808751","display_name":"Yuan-Kai Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yuan-Kai Ho","raw_affiliation_strings":["Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5061699611"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":2.3091,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.89536682,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"32","issue":null,"first_page":"395","last_page":"400"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.804411768913269},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7372872829437256},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6856808662414551},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6752035021781921},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6409332752227783},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6367403268814087},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5609639883041382},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.48194265365600586},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.47905978560447693},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44595766067504883},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.4313294291496277},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3610216975212097},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2540668249130249},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13692015409469604},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.0709892213344574}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.804411768913269},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7372872829437256},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6856808662414551},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6752035021781921},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6409332752227783},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6367403268814087},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5609639883041382},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.48194265365600586},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.47905978560447693},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44595766067504883},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.4313294291496277},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3610216975212097},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2540668249130249},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13692015409469604},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0709892213344574},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2010.5419850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W113756607","https://openalex.org/W1507707340","https://openalex.org/W1974610062","https://openalex.org/W1984588379","https://openalex.org/W1985843314","https://openalex.org/W1997263601","https://openalex.org/W2023981464","https://openalex.org/W2064086982","https://openalex.org/W2096746526","https://openalex.org/W2122533670","https://openalex.org/W2122944491","https://openalex.org/W2136964362","https://openalex.org/W2154363431","https://openalex.org/W2158130267","https://openalex.org/W3143262395","https://openalex.org/W3154674285","https://openalex.org/W3209981646","https://openalex.org/W4230442644","https://openalex.org/W4237096326","https://openalex.org/W4244436417","https://openalex.org/W6604641522","https://openalex.org/W6649575675"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2144282137","https://openalex.org/W2127892766","https://openalex.org/W2617666058","https://openalex.org/W3006003651","https://openalex.org/W2384600254","https://openalex.org/W2090213929","https://openalex.org/W1490763633"],"abstract_inverted_index":{"In":[0,81],"high-performance":[1],"nanometer":[2],"synchronous":[3],"chip":[4],"design,":[5],"a":[6,24,35,86,113],"buffered":[7],"clock":[8,20,42,92],"tree":[9],"with":[10,99,108,136],"high":[11],"tolerance":[12],"of":[13,75,122],"process":[14,76],"variations":[15],"is":[16,47,55],"essential.":[17],"The":[18,41],"nominal":[19,101,147],"skew":[21,102,148],"always":[22],"plays":[23],"crucial":[25],"role":[26],"in":[27],"determining":[28],"circuit":[29],"performance":[30],"and":[31,103,128,149],"thus":[32],"should":[33],"be":[34],"first-order":[36],"objective":[37,70],"for":[38,145,157],"clock-tree":[39,79,117,123],"synthesis.":[40,80],"latency":[43,49],"range":[44],"(CLR),":[45],"which":[46,89,120],"the":[48,58,67,73,109,137,141,154,158],"difference":[50],"under":[51],"different":[52],"supply":[53],"voltages,":[54],"defined":[56],"by":[57,94],"2009":[59,159],"ACM":[60],"ISPD":[61,160],"Clock":[62,161],"Network":[63,162],"Synthesis":[64,163],"Contest":[65],"as":[66],"major":[68],"optimization":[69],"to":[71,152],"measure":[72],"effects":[74],"variation":[77],"on":[78],"this":[82],"paper,":[83],"we":[84,111],"propose":[85],"three-level":[87],"framework":[88,135],"effectively":[90],"constructs":[91],"trees":[93],"performing":[95],"blockage-avoiding":[96],"buffer":[97],"insertion":[98],"both":[100,146],"CLR":[104],"minimization.":[105],"To":[106],"cope":[107],"objectives,":[110],"present":[112],"novel":[114],"three-stage":[115],"TTR":[116,138],"construction":[118],"algorithm":[119,139],"consists":[121],"Topology":[124],"Generation,":[125],"Tapping-Point":[126],"Determination,":[127],"Routing.":[129],"Experimental":[130],"results":[131],"show":[132],"that":[133],"our":[134],"achieves":[140],"best":[142],"average":[143],"quality":[144],"CLR,":[150],"compared":[151],"all":[153],"participating":[155],"teams":[156],"Contest.":[164]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}