{"id":"https://openalex.org/W4247329023","doi":"https://doi.org/10.1109/aspdac.2010.5419803","title":"Statistical timing verification for transparently latched circuits through structural graph traversal","display_name":"Statistical timing verification for transparently latched circuits through structural graph traversal","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W4247329023","doi":"https://doi.org/10.1109/aspdac.2010.5419803"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2010.5419803","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064553444","display_name":"Xingliang Yuan","orcid":"https://orcid.org/0000-0002-3701-4946"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xingliang Yuan","raw_affiliation_strings":["Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100404656","display_name":"Jia Wang","orcid":"https://orcid.org/0000-0002-6159-6085"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jia Wang","raw_affiliation_strings":["Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I180949307"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"663","last_page":"668"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/tree-traversal","display_name":"Tree traversal","score":0.7660081386566162},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7479612827301025},{"id":"https://openalex.org/keywords/graph-traversal","display_name":"Graph traversal","score":0.6105822324752808},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.527230441570282},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.47386837005615234},{"id":"https://openalex.org/keywords/bounded-function","display_name":"Bounded function","score":0.46432986855506897},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.425004780292511},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4139585494995117},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.39373305439949036},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.365130752325058},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16919437050819397},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.11396491527557373}],"concepts":[{"id":"https://openalex.org/C140745168","wikidata":"https://www.wikidata.org/wiki/Q1210082","display_name":"Tree traversal","level":2,"score":0.7660081386566162},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7479612827301025},{"id":"https://openalex.org/C96333769","wikidata":"https://www.wikidata.org/wiki/Q907955","display_name":"Graph traversal","level":3,"score":0.6105822324752808},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.527230441570282},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.47386837005615234},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.46432986855506897},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.425004780292511},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4139585494995117},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.39373305439949036},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.365130752325058},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16919437050819397},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.11396491527557373},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2010.5419803","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1952815481","https://openalex.org/W1967709031","https://openalex.org/W2002525234","https://openalex.org/W2113557950","https://openalex.org/W2136328167","https://openalex.org/W2143847170","https://openalex.org/W2163262735","https://openalex.org/W2180470884","https://openalex.org/W3151924457","https://openalex.org/W4233009716","https://openalex.org/W4246219036","https://openalex.org/W6641884055","https://openalex.org/W6662063287","https://openalex.org/W6676980722","https://openalex.org/W6680337182","https://openalex.org/W7034514939"],"related_works":["https://openalex.org/W2200188075","https://openalex.org/W4252596799","https://openalex.org/W4254594467","https://openalex.org/W4230405657","https://openalex.org/W244044452","https://openalex.org/W2552915643","https://openalex.org/W3213135344","https://openalex.org/W170547082","https://openalex.org/W3183956626","https://openalex.org/W2136735429"],"abstract_inverted_index":{"Level-sensitive":[0],"transparent":[1],"latches":[2],"are":[3,59,64],"widely":[4],"used":[5],"in":[6,51],"high-performance":[7],"sequential":[8],"circuit":[9,20],"designs.":[10],"Under":[11],"process":[12],"variations,":[13],"the":[14,36,42,45,52,79,119],"timing":[15,37,55,90],"of":[16,44,47,109],"a":[17,48,98,106],"transparently":[18],"latched":[19],"will":[21],"adapt":[22],"random":[23],"delays":[24],"at":[25],"runtime":[26],"due":[27],"to":[28,34,40,82],"time":[29],"borrowing.":[30],"The":[31],"central":[32],"problem":[33],"determine":[35],"yield":[38],"is":[39,122],"compute":[41,83],"probability":[43,85],"presence":[46],"positive":[49],"cycle":[50],"latest":[53],"latch":[54],"graph.":[56],"Existing":[57],"algorithms":[58],"either":[60],"optimistic":[61],"since":[62],"cycles":[63,96],"omitted":[65],"or":[66],"require":[67],"iterations":[68],"that":[69,118],"cannot":[70],"be":[71],"polynomially":[72],"bounded.":[73],"In":[74],"this":[75],"paper,":[76],"we":[77],"present":[78],"first":[80],"algorithm":[81],"such":[84],"based":[86],"on":[87],"block-based":[88],"statistical":[89,110],"analysis":[91],"that,":[92],"first,":[93],"covers":[94],"all":[95],"through":[97],"structural":[99],"graph":[100],"traversal,":[101],"and":[102,112,124],"second,":[103],"terminates":[104],"within":[105],"polynomial":[107],"number":[108],"\u00bfsum\u00bf":[111],"\u00bfmax\u00bf":[113],"operations.":[114],"Experimental":[115],"results":[116],"confirm":[117],"proposed":[120],"approach":[121],"effective":[123],"efficient.":[125]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}