{"id":"https://openalex.org/W3142628388","doi":"https://doi.org/10.1109/aspdac.2010.5419801","title":"Statistical time borrowing for pulsed-latch circuit designs","display_name":"Statistical time borrowing for pulsed-latch circuit designs","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W3142628388","doi":"https://doi.org/10.1109/aspdac.2010.5419801","mag":"3142628388"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2010.5419801","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108744170","display_name":"Seungwhun Paik","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seungwhun Paik","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067556633","display_name":"Lee-Eun Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Lee-eun Yu","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7711,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.86802974,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"675","last_page":"680"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5973372459411621},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.5409231781959534},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5198341012001038},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5047892332077026},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5036055445671082},{"id":"https://openalex.org/keywords/variable","display_name":"Variable (mathematics)","score":0.4950091242790222},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.4576394557952881},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4574034512042999},{"id":"https://openalex.org/keywords/pulse","display_name":"Pulse (music)","score":0.438210129737854},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4109693467617035},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.36842745542526245},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3009742796421051},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17333179712295532},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.15333285927772522},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.1349954903125763},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12297362089157104},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10634449124336243}],"concepts":[{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5973372459411621},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.5409231781959534},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5198341012001038},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5047892332077026},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5036055445671082},{"id":"https://openalex.org/C182365436","wikidata":"https://www.wikidata.org/wiki/Q50701","display_name":"Variable (mathematics)","level":2,"score":0.4950091242790222},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.4576394557952881},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4574034512042999},{"id":"https://openalex.org/C2780167933","wikidata":"https://www.wikidata.org/wiki/Q1550652","display_name":"Pulse (music)","level":3,"score":0.438210129737854},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4109693467617035},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.36842745542526245},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3009742796421051},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17333179712295532},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.15333285927772522},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.1349954903125763},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12297362089157104},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10634449124336243},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2010.5419801","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1507979178","https://openalex.org/W1508076293","https://openalex.org/W1518236483","https://openalex.org/W2113002954","https://openalex.org/W2118482092","https://openalex.org/W2125117969","https://openalex.org/W4236709666","https://openalex.org/W4240810344","https://openalex.org/W6630610901","https://openalex.org/W6647121864"],"related_works":["https://openalex.org/W3167886223","https://openalex.org/W2098694303","https://openalex.org/W2118365745","https://openalex.org/W3217430545","https://openalex.org/W1493505771","https://openalex.org/W1621928919","https://openalex.org/W4299458603","https://openalex.org/W2110487025","https://openalex.org/W2074526596","https://openalex.org/W4242010157"],"abstract_inverted_index":{"Pulsed-latch":[0],"inherits":[1],"the":[2,12,28,72,88,94,119,145,151,163,179,186,199,209],"advantage":[3,13,25],"of":[4,14,40,44,49,54,75,90,112,147,205],"latch":[5,99],"in":[6,16,106,202,215],"less":[7],"sequencing":[8],"overhead":[9],"while":[10,208],"taking":[11],"flip-flop":[15],"its":[17],"convenience":[18],"during":[19],"timing":[20,134],"analysis.":[21],"Even":[22],"though":[23],"this":[24,78,107,175],"comes":[26],"from":[27],"fact":[29],"that":[30,86],"pulsed-latch":[31,76],"uses":[32],"a":[33,41,55,65,83],"short":[34],"pulse,":[35],"it":[36],"is":[37,62,68,79,104,136,170,176],"still":[38],"capable":[39],"small":[42],"amount":[43,89],"time":[45,91,149],"borrowing.":[46],"A":[47,101],"problem":[48,108],"allocating":[50],"pulse":[51,114],"width":[52,61],"(out":[53,204],"few":[56],"predefined":[57],"widths),":[58],"where":[59],"each":[60,98],"modeled":[63],"by":[64,93,156,189],"random":[66,84],"variable,":[67],"formulated":[69],"for":[70],"minimizing":[71],"clock":[73,152,187],"period":[74,153,188],"circuits;":[77],"equivalent":[80],"to":[81,132,144,178,197],"assigning":[82],"variable":[85],"represents":[87],"borrowed":[92],"combinational":[95],"block":[96],"between":[97],"pair.":[100],"statistical":[102],"approach":[103],"important":[105],"because":[109],"assuming":[110],"+3\u00bf":[111],"all":[113],"widths":[115],"does":[116],"not":[117],"represent":[118],"worst":[120],"case.":[121],"An":[122],"allocation":[123],"algorithm":[124,131],"called":[125,182],"SPWA":[126],"as":[127,129],"well":[128],"an":[130],"compute":[133],"yield":[135,164,200,210],"proposed.":[137],"In":[138],"experiments":[139],"with":[140],"45-nm":[141],"technology,":[142],"compared":[143,177],"case":[146],"no":[148],"borrowing,":[150],"was":[154],"reduced":[155,185],"12.2%":[157],"and":[158,172,191],"11.7%":[159],"on":[160],"average":[161],"when":[162],"constraint":[165],"Y":[166],"<sub":[167],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[168],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">c</sub>":[169],"0.85":[171],"0.95,":[173],"respectively;":[174],"deterministic":[180],"counterpart":[181],"DPWA,":[183],"which":[184],"7.6%":[190],"7.3%.":[192],"More":[193],"importantly,":[194],"DPWA":[195],"failed":[196],"satisfy":[198],"constraints":[201,211],"four":[203],"eleven)":[206],"circuits":[207],"were":[212],"always":[213],"satisfied":[214],"SPWA.":[216]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}